PUBLICATIONS (1995 – Mar. 2024)

Journal Paper (171 papers)

2024

  1. Yu‑Cheng Hsieh, Yu‑Cheng Lin, Yao‑Hung Huang, Yu‑Der Chih, Jonathan Chang, Chrong Jung Lin, Ya-Chin King, “High-density via RRAM cell with multi-level setting by current compliance circuits,” in Discover Nano vol.19, no. 54, 25 March 2024.
  2. Siao-Ping Sing, Ya-Ching Wang, Wei-Hwa Lin, Yue-Der Chih, Yih Wang, Ya-Chin King, and Chrong Jung Lin, “A New High Density 3D Stackable Via RRAM for Computing-in-Memory SOC Applications,” in IEEE Transactions on Electron Devices (TED)(Early Access ), pp. 1-5, Feb. 2024.
  3. Yao-Hung Huang, Hsin-Yuan Yu, Yue-Der Chih, Yih Wang, Ya-Chin King, and Chrong Jung Lin, “CMOS-Compatible Embedded Artificial Synaptic Device (eASD) for Neuromorphic Computing and AI Applications,” in IEEE Transactions on Electron Devices (TED), vol. 71, no. 2, pp. 1313-1319, Feb. 2024.
  4. Yu-Cheng Lin, Yao-Hung Huang, Kai-Ching Chuang, Yu-Der Chih, Jonathan Chang, Chrong-Jung Lin and Ya-Chin King, “Application of twin-bit self-rectifying via RRAM with unique diode state in cross-bar arrays by advanced CMOS Cu BEOL process,” in Japanese Journal of Applied Physics (JJAP), vol. 63, no. 2, Jan. 2024.

2023

  1. Li-Yu Yeh, Ya-Lin Chang, Yue-Der Chih, Jonathan Chang, Chrong-Jung Lin, Ya-Chin King, “3-D Stackable Offset-Via Antifuse by Cu BEOL Process in Advanced CMOS Technologies,” in IEEE Transactions on Electron Devices (TED), vol. 70, no. 12, pp. 6273-6278, Dec. 2023.
  2. Wei Chang, Chien-Ping Wang, Yao-Hung Huang, Burn Jeng Lin, Pin-Jiun Wu, Jiaw-Ren Shih, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin, Ya-Chin King, “4K Detectors Array for On-Wafer EUV Imaging in Lithography Control Beyond 5-nm Node,” in IEEE Transactions on Electron Devices (TED), vol. 70, no. 11, pp. 5713-5719, Nov. 2023.
  3. Yao-Hung Huang, Chrong-Jung Lin, Ya-Chin King, “A study of hydrogen plasma-induced charging effect in EUV lithography systems,” Discover Nano vol.18, no. 22, 20 June 2023.
  4. Wei-Hwa Lin, Han-Lin Huang, Pin-Jiun Wu, Chrong-Jung Lin, Ya-Chin King, “CMOS Compatible 2T Pixel for On-wafer in-situ EUV Detection,” in Discover Nano vol.18, no. 88, 20 June 2023.
  5. Ming-Shyue Yeh, Ya-Ching Wang, Yao-Hung Huang, Jiaw-Ren Shih, Yue-Der Chih, Jonathan Chang, Chrong-Jung Lin, Ya-Chin King, “Multilevel Fully Logic-Compatible Latch Array for Computing-in-Memory,” in IEEE Transactions on Electron Devices (TED), vol. 70, no. 4, pp. 2001-2008, April 2023.

2022

  1. Kai-Wei Yang, Ting Gan, Jiaw-Ren Shih, Chrong Jung Lin, Ya-Chin King,“Polarity and Patterning Effect on Plasma Charging Levels by Metal-Gate Coupled Recorder Arrays,” in IEEE Transactions on Electron Devices (TED), vol. 69, no. 12, pp. 6971-6976, Oct. 2022.
  2. Ming-te Lin, Kai-Wei Yang, Ya-Chin King, “Evaluation of stability and robustness of poly-Si resistors with different dopant concentrations,” in Japanese Journal of Applied Physics (JJAP), vol. 61, May 2022.
  3. Ying-Chun Shen, Chien-Ping Wang, Kun-Lin Liou, Po-Hung Tan, Yi-Chung Wang, Shu-Chi Wu, Tzu-Yi Yang, Yi-Jen Yu, Tsung-Yu Chiang, Yue-Der Chih, Jonathan Chang, Jiaw-Ren Shih, Chrong Jung Lin, Ya-Chin King* and Yu-Lun Chueh*, “Multifunctional Ion-Sensitive Floating Gate Fin Field-Effect Transistor with Three-Dimensional Nanoseaweed Structure by Glancing Angle Deposition Technology,” in Small, vol. 18, no. 5, pp. 2104168, Feb. 2022.
  4. Chien-Ping Wang, Burn Jeng Lin, Pin-Jiun Wu, Jiaw-Ren Shih, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin and Ya-Chin King*, “Embedded Micro-detectors for EUV Exposure Control in FinFET CMOS Technology,” in Nanoscale Research Letters (NRL), vol. 17, pp. 5, Jan. 2022.

2021

  1. Po-Hung Tan, Che-Hao Hsu, Ying-Chun Shen, Chien-Ping Wang, Kun-Lin Liou, Jiaw-Ren Shih, Chrong Jung Lin, Ling Lee, Kuangye Wang, Hong-Min Wu, Tsung-Yu Chiang, Yue-Der Chih, Jonathan Chang, Ya-Chin King* and Yu-Lun Chueh*, “Complementary Metal–Oxide–Semiconductor Compatible 2D Layered Film-Based Gas Sensors by Floating-Gate Coupling Effect,” in Advanced Functional Materials (AFM), pp. 2108878, Dec. 2021.
  2. Chien-Ping Wang, Wei-Hwa Lin, Burn Jeng Lin, Jiaw-Ren Shih, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin and Ya-Chin King*, “Battery-Less Electronic Layer Detectors Array (ELDA) for In-Tool DUV Detection by FinFET CMOS Technology,” in IEEE Transactions on Electron Devices (TED), vol. 68, no. 10, pp. 4972-4976, Oct. 2021.
  3. Shi Jiun Wang, Chih-An Yang, Burn Jeng Lin, Chrong-Jung Lin and Ya-Chin King*, “On-Wafer Electron Beam Detectors by Floating-Gate FinFET Technologies,” in IEEE Transactions on Electron Devices (TED), vol. 68, no. 9, pp. 4651-4655, Sept. 2021.
  4. Yun-Feng Kao, Jiaw-Ren Shih, Chrong Jung Lin and Ya-Chin King*, “An Early Detection Circuit for Endurance Enhancement of Backfilled Contact Resistive Random Access Memory Array,” in Nanoscale Research Letters (NRL), vol. 16, pp. 114, July 2021.
  5. Yi-Jie Chao, Kai-Wei Yang, Chi Su, Chrong-Jung Lin and Ya-Chin King*, “Wide range detector of plasma induced charging effect for advanced CMOS BEOL processes,” in Nanoscale Research Letters (NRL), vol. 16, pp. 112, July 2021.
  6. Ming-te Lin, Ya-Chin King, “A Study of the Nonlinear Capacitance Variation in Inter Level Copper and Low-k Interconnect Structure,” in IEEE Transactions on Electron Devices (TED), vol. 21, pp. 207-214, Jun 2021.
  7. Chun-Yu Chuang, Chrong-Jung Lin, Ya-Chin King, “Design and optimization of multiple-time programmable memory cell by advanced CMOS FinFET technologies,” in Japanese Journal of Applied Physics (JJAP), vol. 60, May 2021.
  8. Chien-Ping Wang, Burn Jeng Lin, Jiaw-Ren Shih, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin and Ya-Chin King*, “Detectors Array for In Situ Electron Beam Imaging by 16-nm FinFET CMOS Technology,” in Nanoscale Research Letters (NRL), vol. 16, pp. 93, May 2021.

2020

  1. Yu-De Lin, Po-Chun Yeh, Pei-Jer Tzeng, Tuo-Hung Hou, Chih-I Wu, Ya-Chin King, Chrong-Jung Lin, “Promising Engineering Approaches for Improving the Reliability of HfZrOx 2-D and 3-D Ferroelectric Random Access Memories,” in IEEE Transactions on Electron Devices (TED), vol. 67, PP 5479-5483, Dec 2020.
  2. Chieh Lee, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin and Ya-Chin King*, “Memory-Logic Hybrid Gate with 3-D Stackable Complementary Latches,” in IEEE Transactions on Electron Devices (TED), vol. 67, no. 8, pp. 3109-3114, Aug. 2020.
  3. Wei-Chung Zhuang, Ching-Ting Chien, Chrong Jung Lin and Ya-Chin King*, “Self-clamping Programming in Narrow-bridge Floating Gate Cells for Multi-Level Logic Non-volatile Memory Applications,” in IEEE Journal of the Electron Devices Society (JEDS), vol. 8, pp. 681-685, June 2020.
  4. Chi Su*, Yi-Pei Tsai, Chrong-Jung Lin and Ya-Chin King, “Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL Processes,” in Nanoscale Research Letters (NRL), vol. 15, pp. 96, May 2020.
  5. Chien-Ping Wang, Yi-Pei Tsai, Burn Jeng Lin, Zheng-Yong Liang, Po-Wen Chiu, Jiaw-Ren Shih, Chrong Jung Lin and Ya-Chin King*, “On-Wafer FinFET-Based EUV/eBeam Detector Arrays for Advanced Lithography Processes,” in IEEE Transactions on Electron Devices (TED), vol. 67, no. 6, pp. 2406-2413, April 2020.
  6. Yun-Feng Kao, Chrong-Jung Lin and Ya-Chin King*, “Reset Variability in Backfilled Resistive Random Access Memory and Its Correlation to Low Frequency Noise in Read,” in IEEE Journal of the Electron Devices Society (JEDS), vol. 8, pp. 465-473, April 2020.
  7. Cheng-Xin Xue, Wei-Hao Chen, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Tsung-Yuan Huang, Ting-Wei Chang, Tung-Cheng Chang, Hui-Yao Kao, Yen-Cheng Chiu, Chun-Ying Lee, Ya-Chin King, Chrong-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang, “Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors,” in IEEE Transactions on Electron Devices (TED), vol. 55, pp. 203-215, Jan. 2020.

2019

  1. Po-Shao Yeh, Chih-An Yang, Yi-Hong Chang, Yue-Der Chih, Chrong-Jung Lin and Ya-Chin King*, “Self-Convergent Trimming SRAM True Random Number Generation with In-Cell Storage,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 54, no. 9, pp. 2614-2621, Sept. 2019.
  2. Yi-Pei Tsai, Jiaw-Ren Shih, Ya-Chin King, and Chrong-Jung Lin*, “Plasma Charge Accumulative Model in Quantitative FinFET Plasma Damage,” in IEEE Transactions on Electron Devices (TED), vol. 66, no. 8, pp. 3492-3497, Aug. 2019.
  3. Chien-Ping Wang, Ying-Chun Shen, Peng-Chun Liou, Yu-Lun Chueh, Yue-Der Chih, Jonathan Chang, Chrong-Jung Lin and Ya-Chin King*, “Dynamic pH Sensor with Embedded Calibration Scheme by Advanced CMOS FinFET Technology,” in Sensors, vol. 19, no. 7, pp. 1585, April 2019.
  4. Ren-Jay Kuo, Fu-Cheng Chang, Ya-Chin King* and Chrong-Jung Lin, “Antifuse OTP Cell in a Cross-Point Array by Advanced CMOS FinFET Process,” in IEEE Transactions on Electron Devices (TED) 66, no. 4, pp. 1729-1733, April 2019.
  5. Zih-Hong Chen, Po-Hsiang Huang, Chien-Ping Wang, Yu-Der Chih, Chrong-Jung Lin and Ya-Chin King*, “Embedded Near-Infrared Sensor with Tunable Sensitivity for Nanoscale CMOS Technologies,” in IEEE Sensors Journal (SJ), vol. 19, no. 3, pp. 933-939, Feb.1, 2019.
  6. Chih Yuan Chen*, Chrong-Jung Lin and Ya-Chin King, “RTN and Annealing Related to Stress and Temperature in FIND RRAM Array,” in Nanoscale Research Letter (NRL), vol. 14, pp. 12, Jan 2019.

2018

  1. Yu-Fan Chiang, Wei-Yu Chien, Yue-Der Chih, Jonathan Chang, Chrong-Jung Lin* and Ya-Chin King* “FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems,” in Integration the VLSI journal, Dec. 2018.
  2. Yun-Feng Kao, Wei Cheng Zhuang, Chrong-Jung Lin and Ya-Chin King*, “A Study of the Variability in Contact Resistive Random Access Memory by Stochastic Vacancy Model,” in Nanoscale Research Letter (NRL), vol. 13, pp. 213, July 2018.
  3. Yi-Pei Tsai, Peng-Chun Liou, Chrong Jung Lin and Ya-Chin King*, “Plasma Charging Effect on the Reliability of Copper BEOL Structures in Advanced FinFET Technologies,” in IEEE Journal of the Electron Devices Society (JEDS), vol. 6, pp. 875-883, July 2018.
  4. Tai-Min Wang, Wei-Yu Chien, Chia-Ling Hsu, Chrong Jung Lin and Ya-Chin King*, “P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors,” in Japanese Journal of Applied Physics (JJAP), vol. 57, no. 4S, Mar. 2018.
  5. Yi-Hong Shih, Meng-Yin Hsu, Ya-Chin King* and Chrong Jung Lin, “Twin-bit via resistive random access memory in 16 nm FinFET logic technologies,” in Japanese Journal of Applied Physics (JJAP), vol. 57, no. 4S, Mar. 2018.

2017

  1. Zhibo Wang, Yongpan Liu*, Albert Lee, Fang Su, Chieh-Pu Lo, Zhe Yuan, Jinyang Li, Chien-Chen Lin, Wei-Hao Chen, Hsiao-Yun Chiu, Wei-En Lin, Ya-Chin King, Chrong-Jung Lin, Pedram Khalili Amiri, Kang-Lung Wang, Meng-Fan Chang and Huazhong Yang, “A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4times Faster Clock Frequency and > 6times Higher Restore Speed,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 10, pp. 2769-2785, Oct. 2017.
  2. Yi-Pei Tsai*, Ting-Huan Hsieh, Chrong Jung Lin and Ya-Chin King, “Charge Splitting In Situ Recorder (CSIR) for Real-Time Examination of Plasma Charging Effect in FinFET BEOL Processes,” in Nanoscale Research Letters (NRL), vol. 12, no. 1, pp. 534, Sep. 2017.
  3. Albert Lee, Chieh-Pu Lo, Chien-Chen Lin, Wei-Hao Chen, Kuo-Hsiang Hsu, Zhibo Wang, Fang Su, Zhe Yuan, Qi Wei, Ya-Chin King, Chrong-Jung Lin, Hochul Lee, Pedram Khalili Amiri, Kang-Lung Wang, Yu Wang, Huazhong Yang, Yongpan Liu, and Meng-Fan Chang*, “A ReRAM-Based Nonvolatile Flip-Flop with Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 52, no. 8, pp. 2194-2207, Aug. 2017.
  4. Meng-Yin Hsu*, Chu-Feng Liao, Yi-Hong Shih, Chrong Jung Lin and Ya-Chin King, “A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process,” in Nanoscale Research Letters (NRL), vol. 12, no. 1, pp. 418, June. 2017.
  5. Meng-Yin Hsu, Yi-Hong Shih, Yue-Der Chih, Chrong Jung Lin and Ya-Chin King*, “Gate contact resistive random access memory in nano scaled FinFET logic technologies,” in Japanese Journal of Applied Physics (JJAP), vol. 56, no. 4S, Mar. 2017.
  6. Yun Feng Kao, Wei Ting Hsieh, Chun Che Chen, Ya-Chin King* and Chrong Jung Lin, “Statistical analysis of the correlations between cell performance and its initial states in contact resistive random access memory cells,” in Japanese Journal of Applied Physics (JJAP), vol. 56, no. 4S, Mar. 2017.
  7. Bo-Rong Huang, Fan-Hsuan Meng,  Ya-Chin King* and  Chrong Jung Lin, “Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells,” in Japanese Journal of Applied Physics (JJAP),  vol. 56,  no. 4S, Mar. 2017.
  8. Chia-Ling Hsu, Chu-Feng Liao, Wei Yu Chien, Yue-Der Chih, Chrong Jung Lin*and Ya-Chin King, “Differential multiple-time-programmable memory cells by laterally coupled floating metal gate fin field-effect transistors,” in Japanese Journal of Applied Physics (JJAP), vol. 56, no. 4S, Feb. 2017.

2016

  1. Dai Yan Wu, Shuai Fan Chen, Chrong-Jung Lin, and Ya-Chin King*, “Dummy Read Scheme for Lifetime Improvement of MLC NAND Flash Memories,” in IEEE Transactions on Device and Materials Reliability (TDMR), vol. 16, no. 4, pp. 583-587, Dec. 2016.
  2. Kai Ping Huang, Hsin Wei Pan, Shih Yu Chen, Ping Chun Peng, Cheng-Hsiung Kuo, Yue-Der Chih, Chrong Jung Lin, and Ya-Chin King* “1-kb FinFET Dielectric Resistive Random Access Memory Array in 1times nm CMOS Logic Technology for Embedded Nonvolatile Memory Applications,” in IEEE Transactions on Electron Devices (TED), vol. 63, no. 11, pp. 4273-4278, Nov. 2016.
  3. Hung-Yu Chen, Hsien Hao Chen, Ya-Chin King, and Chrong Jung Lin, “Investigation of Set/Reset Operations in CMOS Logic-Compatible Contact Backfilled RRAMs,” in IEEE Transactions on Device and Materials Reliability (TDMR), vol. 16, no. 3, pp. 370-375, Sep. 2016.
  4. Yu-Zheng Chen, Jo En Yuan, Chrong Jung Lin, and Ya-Chin King*, “Multilevel Antifuse Cells by Progressive Rupturing of the High- kappa Gate Dielectric in FinFET Technologies,” in IEEE Electron Device Letters (EDL), vol. 37, no. 9, pp. 1120-1122, Sep. 2016.
  5. Yi-Pei Tsai, Chun-Hsiung Wu, Chrong Jung Lin, and Ya-Chin King, “Wafer-Level Mapping of Plasma-Induced Charging Effect by On-Chip In Situ Recorders in FinFET Technologies,” in IEEE Transactions on Electron Devices (TED), vol. 63, no. 6, pp. 2497-2502, June 2016.
  6. Shu-En Chen, Meng-Yin Hsu, Chu-Feng Liao, Chrong Jung Lin, and Ya-Chin King*, “Titanium-Oxide-Based Slot Contact RRAM in Nanoscaled FinFET Logic Technologies,” in IEEE Electron Device Letters (EDL), vol. 37, no. 4, pp. 393-395, April 2016.
  7. Ping Chun Peng, Yu-Zheng Chen, Woan Yun Hsiao, Kuang-Hsin Chen, Ching-Pin Lin, Bor-Zen Tien, Tzong-Sheng Chang, Chrong Jung Lin, and Ya-Chin King*, “High-Density FinFET One-Time Programmable Memory Cell With Intra-Fin-Cell-Isolation Technology”, Japanese Journal of Applied Physics (JJAP), vol. 55, no. 4S, March, 2016.
  8. Teng-Hao Yeh, Wei-Chen Chen, Tzu-Hsuan Hsu, Pei-Ying Du, Chih-Chang Hsieh, Hang-Ting Lue, Yen-Hao Shih, Ya-Chin King, and Chih-Yuan Lu, “Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND”, IEEE Transactions on Electron Devices (TED), vol. 63, no. 3, pp. 1047-1053,Mar., 2016.
  9. Fan-Hsuan Meng, Po-Yen Lin, Yu-Lun Chiu, Bo-Rong Huang, Chrong Jung Lin, and Ya-Chin King, “Effect of three-dimensional current distribution on characterizing parasitic resistance of FinFETs,” Japanese Journal of Applied Physics (JJAP), vol. 55, no. 4S, March, 2016.

2015

  1. Lin, Po-Yen; Chiu, Yu-Lun; Sung, Yuh-Te; Chen, J.; Chang, Tzong-Sheng; Ya-Chin King*; Chrong Jung Lin, “On-chip Recovery Operation for Self-Aligned Nitride Logic Non-Volatile Memory Cells in High-K Metal Gate CMOS Technology,” in IEEE Journal of the Electron Devices Society (JEDS), vol.PP, no.99, pp.1-1, Nov. 2015.
  2. Ping Chun Peng; Yu-Zheng Chen; Woan Yun Hsiao; Kuang-Hsin Chen; Ching-Pin Lin; Bor-Zen Tien; Tzong-Sheng Chang; Chrong Jung Lin; Ya-Chin King*, “High-Density FinFET One-Time Programmable Memory Cell With Intra-Fin-Cell-Isolation Technology,” in Electron Device Letters (EDL), IEEE , vol.36, no.10, pp.1037-1039, Oct. 2015.
  3. Shu-En Chen; Yung-Wen Chin; Min-Che Hsieh; Chu-Feng Liao; Tzong-Sheng Chang; Chrong Jung Lin; Ya-Chin King*, “Self-Rectifying Twin-Bit RRAM in 3-D Interweaved Cross-Point Array,” in in IEEE Journal of the Electron Devices Society (JEDS), vol.3, no.4, pp.336-340, July 2015.
  4. Teng-Hao Yeh*, Chen-Jun Wu, Chih-Wei Hu, Wei-Chen Chen, Hang-Ting Lue, Yen-Hao Shih, Ya-Chin King, and Chih-Yuan Lu, “A New String Decoding Scheme for Enhancing Array Block Efficiency of Vertical Gate Type (VG-type) 3D NAND,” in IEEE Electron Device Letters (EDL), vol.36, no. 4, pp. 330-332, Apr. 2015.
  5. Woan Yun Hsiao; Ping Chun Peng; Tzong-Sheng Chang; Yu-Der Chih; Wu-Chin Tsai; Meng-Fan Chang; Tun-Fei Chien; Ya-Chin King; Chrong Jung Lin*, “A New High-Density Twin-Gate Isolation One-Time Programmable Memory Cell in Pure 28-nm CMOS Logic Process,” in IEEE Transactions Electron Devices (TED), vol.62, no.1, pp.121-127, Jan. 2015.

2014

  1. Yu-Cheng Liao; Hsin-Wei Pan; Min-Che Hsieh; Tzong-Sheng Chang; Yu-Der Chih; Ming-Jinn Tsai; Chrong Jung Lin; Ya-Chin King*, “Via Diode in Cu Backend Process for 3D Cross-Point RRAM Arrays,” in IEEE Journal of the Electron Devices Society (JEDS), vol.2, no.6, pp.149-153, Nov. 2014.
  2. Sheng-Yen Chien; Po-Yen Lin; Hung-Yu Chen; Chrong Jung Lin; Ya-Chin King, “Self-Matching SRAM With Embedded OTP Cells in Nanoscale Logic CMOS Technologies,” in IEEE Transactions on Electron Devices (TED), vol.61, no.11, pp.3731-3736, Nov. 2014.
  3. Liang-Shun Chang, Ching-Hua Wang, Kun-Yu Dai, Kuei-Hung Shen, Ming-Jinn Tsai, Chrong Jung Lin, Ya-Chin King*, “Magnetic Wireless Interlayer Transmission Through Perpendicular MTJ for 3-D IC Applications,” in IEEE Transactions on Electron Devices (TED), vol.61, no.7, pp.2480-2485, July 2014.
  4. Meng-Fan Chang*; Chia-Chen Kuo; Shyh-Shyuan Sheu; Chrong Jung Lin; Ya-Chin King; Chen, F.T.; Tzu-Kun Ku; Ming-Jinn Tsai; Jui-Jen Wu; Yue-Der Chih, “Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme,” in IEEE Journal of Solid-State Circuits (JSSC),49, no.4, pp.908-916, April 2014.
  5. Tsung-Yu Tsai*, Ya-Chin King and Chrong Jung Lin, ”Current-mode ambient light sensor for ultralow-power applications” in Japanese Journal of Applied Physics (JJAP), 18 March 2014.
  6. Min-Che Hsieh, Yung-Wen Chin, Yu-Cheng Lin, Yu-Der Chih, Kan-Hsueh Tsai, Ming-Jinn Tsai, Ya-Chin King, and Chrong Jung Lin* , ” A new laterally conductive bridge random access memory by fully CMOS logic compatible process” in Japanese Journal of Applied Physics (JJAP), 6 March 2014.
  7. Zih-Song Wang*; Wei-Shiang Huang; Chih-Yuan Chen; Arakawa, H.; Chrong Jung Lin, “Improvement of Bottom Oxide Thickness Scaling of Inter-Poly Dielectric by Floating Gate Top Plasma Nitridation,” in Electron Device Letters (EDL), IEEE , vol.35, no.2, pp.190-192, Feb. 2014.
  8. Wen Chao Shen, Ching-Hua Wang, Hsin-Wei Pan, Zhi-Sung Yang, Yue Der Chih, Te-Liang Lee, Chiu-Wang Lien, Ya-Chin King and Chrong Jung Lin* , ” A novel high-density embedded AND-type split gate flash memory” in Japanese Journal of Applied Physics (JJAP), 24 February 2014.
  9. Woan Yun Hsiao, Chin Yu Mei, Wen Chao Shen, Yue Der Chih, Ya-Chin King, Chrong Jung Lin*, ” A new 28 nm high-k metal gate CMOS logic one-time programmable memory cell” in Japanese Journal of Applied Physics (JJAP), vol. 53, no. 4S, 7 Feb. 2014.
  10. Liang-Shun Chang*, Chrong Jung Lin and Ya-Chin King, ” Temperature dependent characteristics of the random telegraph noise on contact resistive random access memory” in Japanese Journal of Applied Physics (JJAP), 2 Feb 2014.

2013

  1. Chin Yu Mei, Wen Chao Shen, Chun Hsiung Wu, Yue-Der Chih, Ya-Chin King, Chrong Jung Lin*, Ming-Jinn Tsai, Kan-Hsueh Tsai, and Frederick T. Chen, “28-nm 2T High-K Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes,” IEEE Electron Device Letters (EDL), vol. 34, no. 10, pp. 1253-1255, Oct, 2013.
  2. Meng-Fan Chang, Che-Wei Wu, Chia-Cheng Kuo, Shin-Jang Shen, Sue-Meng Yang, Ku-Feng Lin, Wen-Chao Shen, Ya-Chin King, Chrong Jung Lin, and Yu-Der Chih, “A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro,” IEEE Journal of Solid-State Circuits (JSSC), vol. 48, no. 9, pp. 2250-2259, Sep, 2013.
  3. Wen Chao Shen, Te-Liang Lee, Hsin-Wei Pan, Zhi-Sung Yang, Yue-Der Chih, Chiu-Wang Lien, Ya-Chin King, and Chrong Jung Lin*, “New High-Density Differential Split Gate Flash Memory With Self-Boosting Function,” IEEE Electron Device Letters (EDL), vol. 34, no. 9, pp. 1127-1129, Sep, 2013.
  4. Min-Che Hsieh, Yu-Cheng Lin, Yung-Wen Chin, Tzong-Sheng Chang, Ya-Chin King*, and Chrong Jung Lin, “Characterization of Multilayer Metal Gate Fuse in 28-nm CMOS Logic Technology,” IEEE Electron Device Letters (EDL), vol. 34, no. 9, pp. 1088-1090, Sep, 2013.
  5. Te Liang Lee, Ming Tsang Tsai, Ya Chin King and Chrong Jung Lin*, “A Novel Sub-20 V Contact Gate Metal Oxide Semiconductor Field Effect Transistor with Fully Complementary Metal Oxide Semiconductor Compatible Process,” Japanese Journal of Applied Physics (JJAP), vol. 52, no. 4, pp. 6, Apr, 2013.
  6. Meng-Fan Chang*, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Ya-Chin King, Chrong Jung Lin, Hung-Jen Liao, Yu-Der Chih, and Hiroyuki Yamauchi, “An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory,” IEEE Journal of Solid-State Circuits (JSSC), vol. 48, no. 3, pp. 864-877, Mar, 2013.
  7. Zih-Song Wang, Te-Yuan Yin, Tzung-Hua Ying, Ya-Jui Lee, Chieh-Yi Lu, Hideki Arakawa, and Chrong Jung Lin*, “Impact of Moisture From Passivation on Endurance and Retention of NAND Flash Memory,” IEEE Transactions on Electron Devices (TED), vol. 60, no. 1, pp. 254-259, Jan, 2013.
  8. Liang-Shun Chang, Chien-Yuan Huang, Yuan-Heng Tseng, Ya-Chin King and Chrong Jung Lin*, “Temperature Sensing Scheme Through Random Telegraph Noise in Contact RRAM,” IEEE Electron Device Letters (EDL), vol. 34, no. 1, pp. 12-14, Jan, 2013.

2012

  1. Chien-Yuan Huang, Wen Chao Shen, Yuan-Heng Tseng, Ya-Chin King and Chrong Jung Lin, “A Contact-Resistive Random-Access-Memory-Based True Random Number Generator,” IEEE Electron Device Letters (EDL), vol. 33, no. 8, pp. 1108-1110, Aug, 2012.
  2. Chiu-Wang Lien, Haw-Yun Wu, Cheng-Wei Tsai, Chen-Mei Huang, Yue-Der Chih, Te-Liang Lee, and Chrong Jung Lin, “A New 2T Contact Coupling Gate MTP Memory in Fully CMOS Compatible Process,” IEEE Transactions on Electron Devices (TED), vol. 59, no. 7, pp. 1899-1905, Jul, 2012.
  3. Zih-Song Wang, Ya-Jui Lee, Rex Yang, Ying-Chia Lin, Huei-Haurng Chen, and Chrong Jung Lin, “A New Recess Method for SA-STI NAND Flash Memory,” IEEE Electron Device Letters (EDL), vol. 33, no. 6, pp. 896-898, Jun, 2012.
  4. Chia-Chin Huang, Jalin Ko-Tsung Huang, Chi-Wei Lee, and Chrong Jung Lin, “A CMOS Active Pixel Sensor With Light Intensity Filtering Characteristics for Image Thresholding Application,” IEEE Sensors Journal (SENS J), vol. 12, no. 5, pp. 1289-1293, May, 2012.
  5. Yuan Heng Tseng, Wen Chao Shen and Chrong Jung Lin, “Modeling of Electron Conduction in Contact Resistive Random Access Memory Devices as Random Telegraph Noise,” Journal of Applied Physics (JAP), VOL. 111, NO. 7, April, 2012.
  6. Li-Yu Yang, Min-Che Hsieh, Jheng-Sin Liu, Yung-Wen Chin, and Chrong Jung Lin, “A Highly Scalable Interface Fuse for Advanced CMOS Logic Technologies,” IEEE Electron Device Letters (EDL), VOL. 33, NO. 2, Feb. 2012.

2011

  1. Wen Chao Shen, Yuan Heng Tseng, Y.-D. Chih, and Chrong Jung Lin, “Memristor Logic Operation Gate With Share Contact RRAM Cell,” IEEE Electron Device Letters (EDL), VOL. 32, NO. 12, Dec. 2011.
  2. Haw-Yun Wu, Cheng-Wei Tsai, Chiu-Wang Lien, Y.-D. Chih, and Chrong Jung Lin, “A High Density MTP Cell with Contact Coupling Gates by Pure CMOS Logic Process,” IEEE Electron Device Letters (EDL), vol. 32, no. 10, pp. 1352-1354, Oct, 2011.
  3. Chien Liang Chen and Ya-Chin King, “TiN Thickness Impact on BTI Performance,” IEEE Electron Device Letters (EDL), vol. 32, no. 6, pp. 707-709, Jun, 2011.
  4. Chien-Liang Chen and Ya-Chin King, “TiN Metal Gate Electrode Thickness Effect on BTI and Dielectric Breakdown in HfSiON-Based MOSFETs,” IEEE Transactions on Electron Devices (TED), vol. 58, no. 11, pp. 3736-3742, Nov, 2011.
  5. Tang-Jung Chiu, Jeng Gong, Ya-Chin King, Chih-Cheng Lu, and Hsin Chen, “An Octagonal Dual-Gate Transistor With Enhanced and Adaptable Low-Frequency Noise,” IEEE Electron Device Letters (EDL), vol. 32, no. 1, pp. 9-11, Jan, 2011.
  6. Tang-Jung Chiu, Ya-Chin King, Jeng Gong, Yi-Hung Tsai, and Hsin Chen, “A Resist-Protection-Oxide Transistor With Adaptable Low-Frequency Noise for Stochastic Neuromorphic Computation in VLSI,” IEEE Electron Device Letters (EDL), vol. 32, no. 9, pp. 1293-1295, Sep, 2011.
  7. Ching-Hua Wang, Yi-Hung Tsai, Kai-Chun Lin, Meng-Fan Chang, Ya-Chin King, and Chrong Jung Lin Shyh-Shyuan Sheu, Yu-Sheng Chen, Heng-Yuan Lee, Frederick T. Chen, and Ming-Jinn Tsai, “Three-Dimensional 4F2 ReRAM with Vertical BJT Driver by CMOS Logic Compatible Process,” IEEE Transactions on Electron Devices (TED), vol. 58, no. 8, pp. 2466-2472, Aug, 2011.
  8. Chih-Yang Chen, Chrong Jung Lin, and Ya-Chin King, “A New Sensing Scheme for Sensitivity Enhancement of Low-Temperature Polycrystalline Silicon Photo detectors”, IEEE Sensors Journal (SENS J), Volume: 11 Issue: 6 Pages: 1478-1483, Jun 2011.
  9. Te-Liang Lee, Yi-Hung Tsai, Wun-Jie Lin, Hsiao-Lan Yang, Chiu-Wang Lien, Chrong Jung Lin, and Ya-Chin King, “A New Differential P-Channel Logic-Compatible Multiple-Time Programmable (MTP) Memory Cell With Self-Recovery Operation,” IEEE Electron Devices Letters (EDL), vol. 32, Issue:5, Pages: 587-589, May 2011.
  10. Shou-En Liu, Ming-Jiue Yu, Chang-Yu Lin, Geng-Tai Ho, Chun-Cheng Cheng, Chih-Ming Lai, Chrong Jung Lin, Ya-Chin King, and Yung-Hui Yeh, “Influence of Passivation Layers on Characteristics of a-InGaZnO Thin-Film Transistors”, IEEE Electron Device Letters (EDL), vol. 32, no. 2, pp. 161-163, Feb, 2011.
  11. Yuan Heng Tseng, Chia-En Huang, C.-H. Kuo, Y.-D. Chih, Ya-Chin King, and Chrong Jung Lin, “A New High-Density and Ultrasmall-Cell-Size Contact RRAM (CR-RAM) With Fully CMOS-Logic-Compatible Technology and Circuits”, IEEE Transactions on Electron Devices (TED), vol. 58, no. 1, pp. 53-58, Jan, 2011.

2010

  1. Te-Yu Lee, Chrong Jung Lin, Ya-Chin King , “High-uniformity 2T1C AMOLED panels by a built-in trimming method”, Journal of the Society for Information Display (SID), vol. 18, no. 8, pp. 544-549, Aug, 2010.
  2. Chia-En Huang, Yuan Heng Tseng, Cheng-Hsiung Kuo, Yu-De Chih, Ya-Chin King , Chrong Jung Lin, “Multilevel Antifuse Cells with Programmable Contact in Pure 90 nm Logic Process”, Japanese Journal of Applied Physics (JJAP), vol. 49, no. 1, 2010.
  3. Te-Liang Lee, Yi-Hung Tsai, Wun-Jie Lin, Hsiao-Lan Yang, Chiu-Wang Lien, Chrong Jung Lin, and Ya-Chin King, “A New Differential Logic-Compatible Multiple-Time Programmable Memory Cell”, Japanese Journal of Applied Physics (JJAP), vol. 49, no. 4, 2010.
  4. Chia-En Huang, Ying-Je Chen, Hsun OuYang, Chrong Jung Lin, Ya-Chin King , “Source Side Injection Programmed P-Channel Self-Aligned-Nitride One-Time Programming Cell for 90 nm Logic Nonvolatile Memory Applications”, Japanese Journal of Applied Physics (JJAP), vol. 49, no. 4, 2010.
  5. Sheng-Huei Dai, Jeng-Jie Peng, Chia-Cheng Chen, Chrong Jung Lin, Ya-Chin King , “Lateral Back-to-Back Diode for Low-Capacitance Transient Voltage Suppressor”, Japanese Journal of Applied Physics (JJAP), vol. 49, no. 4, 2010.
  6. Chih-Yang Chen, Chrong Jung Lin, Ya-Chin King, “Integration of Microcoil Magnetic Manipulation with High-Sensitivity Complementary Metal-Oxide-Semiconductor Photosensor Detection in Bio-Analyses”, Japanese Journal of Applied Physics (JJAP), vol. 49, no. 4, 2010.

2009

  1. Chih-Yang Chen, Chien-Yu Huang, Chrong Jung Lin, Ya-Chin King , “A low-temperature polycrystalline-silicon thin-film transistor micro-manipulation array with indium tin oxide micro-coils and real-time detection”, Journal of Micromechanics and Microengineering (JMM), vol. 19, no. 12, Dec, 2009.
  2. Hung-Sheng Shih, Shang-Wei Fang, An-Chi Kang, Ya-Chin King, Chrong Jung Lin, “High program efficiency of p-type floating gate in n-channel split-gate embedded flash memory”, Applied Physics Letters (APL), vol. 93, no. 21, Nov, 2008.
  3. Yi-Hung Tsai, Kai-Chun Lin, Cheng-Hsiung Kuo, Yue-Der Chih, Chrong Jung Lin, Member, IEEE, and Ya-Chin King, “A Nitride-Based P-Channel Logic-Compatible One-Time-Programmable Cell With a New Contact Select Gate”, IEEE Electron Device Letters (EDL), vol. 30, no. 10, pp. 1090-1092, Oct, 2009.
  4. Yi-Hung Tsai, Kai-Chun Lin, Hsin-Yi Chiu, Hung-Sheng Shih, Ya-Chin King, Chrong Jung Lin, “A study of gateless OTP cell using a 45 nm CMOS compatible process”, Solid-State Electronics (Solid-State Electron.), vol. 53, no. 10, pp. 1092-1098, Oct, 2009.
  5. Chia-En Huang, Ying-Je Chen, Han-Chao Lai, Ya-Chin King  and Chrong Jung Lin, “A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process”, IEEE Transactions on Electron Devices (TED), vol. 56, no. 6, pp. 1228-1234, Jun, 2009.
  6. Tzu-Hsuan Hsu, Hang-Ting Lue, Ya-Chin King, Yi-Hsuan Hsiao, Sheng-Chih Lai, Kuang-Yeu Hsieh, Rich Liu, and Chih-Yuan Lu, “Physical Model of Field Enhancement and Edge Effects of FinFET Charge-Trapping NAND Flash Devices,” IEEE Transactions on Electron Devices, vol. 56, no. 6, pp. 1235-1242, Jun, 2009.
  7. Sheng-Huei Dai, Jeng-Jie Peng, Chia-Cheng Chen, Chrong Jung Lin, Ya-Chin King “Low-Capacitance Low-Voltage Transient Voltage Suppressor Using Diode-Activated SiGe Heterojunction Bipolar Transistor in SiGe Heterojunction Bipolar Transistor Bipolar Complementary Metal-Oxide-Semiconductor Process”, Japanese Journal of Applied Physics (JJAP), vol. 48, no. 4, Apr, 2009.
  8. Wen-Jen Chiang, Chrong Jung Lin, Ya-Chin King, An-Thung Cho, Chia-Tien Peng, and Wei-Ming Huang, “Integrated Ambient Light Sensor With Nanocrystalline Silicon on a Low-Temperature Polysilicon Display Panel”, IEEE Transactions on Electron Devices (TED), vol. 56, no. 4, pp. 578-586, Apr, 2009.
  9. Wen-Jen Chiang, Chrong Jung Lin, Ya-Chin King, “Embedded Optical Sensor Using Gate-Body-Tied Thin-Film Transistor on Low-Temperature Poly-Silicon Display Panel”, Electrochemical and Solid State Letters (ESL), vol. 12, no. 5, pp. J51-J53, 2009.

2008

  1. Han-Chao Lai, Chia-En Huang, Ya-Chin King , Chrong Jung Lin, “Novel Self-Aligned Nitride One Time Programming with 2-bit/Cell Based on Pure 90-nm Complementary Metal-Oxide-Semiconductor Logic Technology”, Japanese Journal of Applied Physics (JJAP), vol. 47, no. 11, pp. 8369-8374, Nov, 2008.
  2. Te-Yu Lee, Chih-Chieh Chiu, Yu-Chung Liu, Chih-Chung Liu, Ya-Chin King, and Chrong Jung Lin, “A new embedded one-time-programmable MNOS memory fully compatible to LTPS fabrication for system-on-panel (SOP) applications”, IEEE Electron Device Letters (EDL), vol. 29, no. 8, pp. 906-908, Aug, 2008.
  3. Ying-Je Chen, Chia-En Huang, Hsin-Ming Chen, Han-Chao Lai, J. R. Shih, Kenneth Wu, Ya-Chin King, Member, IEEE, and Chrong Jung Lin, “A novel 2-bit/cell p-channel logic programmable cell with pure 90-nm CMOS technology”, IEEE Electron Device Letters (EDL), vol. 29, no. 8, pp. 938-940, Aug, 2008.
  4. Shih, S. W. Fang, A. C. Kang et al., “High program efficiency of p-type floating gate in n-channel split-gate embedded flash memory,” Applied Physics Letters, vol. 93, no. 21, Nov, 2008.
  5. Hsu, H. T. Lue, W. C. Peng et al., A study of sub-40nm FinFET BE-SONOS NAND flash, New York: IEEE, 2008.
  6. Hsu, H. T. Lue, W. C. Peng et al., High performance and scalable FinFET BE-SONOS device for NAND Flash memory application, New York: IEEE, 2008.
  7. Dai,  Lin, and  C. King, “Leakage suppression of low-voltage transient voltage suppressor,” IEEE Transactions on Electron Devices, vol. 55, no. 1, pp. 206-210, Jan, 2008.
  8. Chiang,  Lin,  C. Kinget al., “Silicon-nanocrystal-based photosensor integrated on low-temperature polysilicon panels,” Journal of the Society for Information Display, vol. 16, no. 7, pp. 777-786, Jul, 2008.
  9. Chen, C. E. Huang, Y. H. Tseng et al., “A new antifuse cell with programmable contact for advance CMOS logic circuits,” IEEE Electron Device Letters, vol. 29, no. 5, pp. 522-524, May, 2008.
  10. Chen, J. J. Wang,  Linet al., “Real-time variable-resolution complementary metal-oxide-semiconductor field-effect transistors image sensor,” Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2756-2760, Apr, 2008.
  11. Chang, H. W. Chang, T. C. Lu et al., “Combining a novel charge-based capacitance measurement (CBCM) technique and split C-V method to specifically characterize the STI stress effect along the width direction of MOSFET devices,” IEEE Electron Device Letters, vol. 29, no. 6, pp. 641-644, Jun, 2008.

2007

  1. Lu S.C., Wu, Z. H., Huang C. E., Hung S. J., Chen M. H., King, Y. C.(2007). “CMOS micromachined grippers with on-chip optical detection. ” Journal of Micromechanics and Microengineering 17(2): 482.

2006

  1. Chang YW, Chang HW, Lu TC, King YC, Ting WC, Ku YHJ, Lu CY, “Charge-based capacitance measurement for bias-dependent capacitance”, IEEE ELECTRON DEVICE LETTERS 27 (5): 390-392 MAY 2006
  2. Lai CH, King YC, Huang SY, “A 1.2-V 0.25um clock output pixel architecture with wide dynamic range and self-offset cancellation”, IEEE SENSORS JOURNAL 6 (2): 398-405 APR 2006
  3. Hsieh SI, Chen HT, Chen YC, Chen CL, King YC. “ MONOS memory in sequential laterally solidified low-temperature poly-Si TFTs” IEEE ELECTRON DEVICE LETTERS 27 (4): 272-274 APR 2006
  4. Lai CH, Lai LW, Chiang WJ, King YC,“A logarithmic response complementary metal oxide semiconductor image sensor with parasitic P-N-P bipolar junction transistor”, JAPANESE JOURNAL OF APPLIED PHYSICS 45 (4B): 3251-3255 APR 2006
  5. Hsieh SI, Chen HT, Chen YC, Chen CL, Lin JX, King YC, “ Reliability and memory characteristics of sequential laterally solidified low temperature polycrystalline silicon thin film transistors with an oxide-nitride-oxide stack gate dielectric”, JAPANESE JOURNAL OF APPLIED PHYSICS 45 (4B): 3154-3158 APR 2006
  6. Hu LC, Kang AC, Shih JR, Lin YF, Wu K, King YC, “Statistical modeling for postcycling data retention of split-gate flash memories”, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 6 (1): 60-66 MAR 2006
  7. Wu MY, Dai SH, Lee KH, Hu SF, King YC,“ Band-to-band tunneling induced substrate hot electron injection (BBISHE) to perform programming for NOR flash memory”, SOLID-STATE ELECTRONICS 50 (3): 309-315 MAR 2006
  8. Chang, Y.-W.; Chang, H.-W.; Lu, T.-C.; King, Y.-C.; Ting, W.; Ku, Y.-H.J.; Lu, C.-Y.; “Interconnect Capacitance Characterization Using Charge-Injection-Induced Error-Free (CIEF) Charge-Based Capacitance Measurement (CBCM)”, IEEE Transactions on Semiconductor Manufacturing, 19(1): 50 – 56 FEB 2006
  9. Wu MY; Dai SH; Hu SF; Yang, E.C.-S.; Hsu, C.C.-H.; King YC; ”Comprehensively study on a ballistic-injection AND-type flash memory cell”, Japanese Journal of Applied Physics, 45(2A): 674-679 FEB. 2006
  10. Wu MY; Dai SH; Hu SF; E.C.-S.; Hsu, C.C.-H.;King, Y.-C.; “Highly scalable ballistic injection AND-type (BiAND) flash memory”, IEEE Transactions on Electron Devices, 53(1): 109 – 111,Jan 2006
  11. Hsieh SI, Chen HT, Chen YC, Chen CL, King YC, “Threshold voltage uniformity enhancement for low-temperature polysilicon thin-film transistors using tilt alignment technique”, ELECTROCHEMICAL AND SOLID STATE LETTERS 9 (7): H57-H60 2006
  12. Chen HT, Chen YC, Lin JX, Hsieh SI, King YC, “Roughness effect on uniformity and reliability of sequential lateral solidified low-temperature polycrystalline silicon thin-film transistor”, ELECTROCHEMICAL AND SOLID STATE LETTERS 9 (8): H81-H83 2006
  13. Hu, L. C., Kang, A. C., Wu, T. Y., Shih, J. R., Lin, Y. F., Wu, K. and King, Y. C.(2006). “Efficient Low-Temperature Data Retention Lifetime Prediction for Split-Gate Flash Memories Using a Voltage Acceleration Methodology.” IEEE Transactions On Device And Materials Reliability 6(4): 528.

2005

  1. Ying-Chieh Chuang; Shih-Fang Chen; Shi-Yu Huang; Ya-Chin King; “Low-cost logarithmic CMOS image sensing by nonlinear analog-to-digital conversion”, IEEE Transactions on Consumer Electronics, Volume 51, Issue 4, Nov. 2005 Page(s):1212 – 121
  2. Kung-Hong Lee, Shih-Cheng Wang, Ya-Chin King, “Self-convergent scheme for logic-process-based multilevel/analog memory”, IEEE Transactions on Electron Devices, Volume 52, Issue 12, December 2005: Page(s):2676-2681
  3. Ling-Chang Hu, An-Chi Kang*, T.I. Wu*, Eric Chen*, J.R. Shih*, H.W. Chin*, Yao-Feng Lin*, Kenneth Wu*, Ya-Chin King, ”Gate stress effect on low temperature data retention characteristics of split-gate flash memories”, Microelectronics Reliability, Volume: 45, Issue: 9-11, Sep.-Nov. 2005: 1331-1336
  4. Wei-Cheng Lin; Tsung-Chien Wu; Yi-Hung Tsai; Long-Jei Du; Ya-Chin King;“Reliability evaluation of class-E and class-a power amplifiers with nanoscaled CMOS technology”, IEEE Transactions on Electron Devices, Volume 52, Issue 7, July 2005: Page(s):1478 – 1483
  5. Cheng-Hsiao Lai, Yueh-Ping Yu; Kung-Hong Lee; Ya-Chin King, “A New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors”, Japanese Journal of Applied Physics, vol. 44, no 4B, April, 2005: 2214-2216
  6. Kung-Hong Lee; Ya-Chin King, “ Embedded Ultra High Density Flash Memory Cell and Corresponding Array Architecture”, Japanese Journal of Applied Physics, vol. 44, no 4B, April, 2005: 2083-2087
  7. Kung-Hong Lee; Ya-Chin King, “High-Density Single-Poly Electrically Erasable Programmable Logic Device for Embedded Nonvolatile Memory Applications”, Japanese Journal of Applied Physics, vol. 44, no 1A, January, 2005:44-49

2004

  1. Wei-Cheng Lin; Long-Jei Du; Ya-Chin King; “Reliability Evaluation and Redesign of LNA”, Microelectronics Reliability, Volume: 44, Issue: 9-11, Sep.-Nov. 2004: 1727-1732
  2. Po-Hao Huang, Hsiu-Yu Cheng, Wen-Jen Chiang, Cheng-Hsiao Lia and Ya-Chin King, “Optimization of The Ultra-Low Dark Current Complementary MOS Image Sensor Using n+ Ring Reset”, Japanese Journal of Applied Physics, vol. 43, no 4B, April 2004:1734-1736
  3. Liang-Wei Lai,, Cheng-Hisiao Lai, Ya-Chin King, “A novel logarithmic response CMOS image sensor with high output voltage swing and in-pixel fixed-pattern noise reduction”, IEEE SENSORS JOURNAL 4 (1): 122-126 FEB 2004

2003

  1. Hsien-Chun Chang, Ya-Chin King, “Tunable Injection Current Compensation Architecture for High Fill-Factor Self-Buffered Active Pixel Sensor”, IEEE Sensor Journal, vol.3, no4, August 2003:525-532
  2. Sing–Rong Lee, Cheng-Hisiao Lai, Ya-Chin King, “A New Sampling Scheme for High Sensitive, Extended Dynamic Range CMOS Imaging Pixel Sensors” , Japanese Journal of Applied Physics, vol. 42, April 2003:2159-2162
  3. Hsiu-Yu Cheng, Ya-Chin King, “A CMOS Image Sensor with Dark-Current Cancellation and Dynamic Sensitivity Operations”, IEEE Transactions on Electron Devices, vol. 50, no. 1, Jan. 2003:91-95

2002

  1. Hai-Ming Lee, Long-Jye Du, Mong-Song Liang, Ya-Chin King, Charles Ching-Hsiang, “A Unified Functional Reliablity Model for N-channel MOSFET with Sub 2nm Gate Oxide”, Japanese Journal of Applied Physics, vol. 41, September 2002: 5546-5550
  2. Hsiu-Yu Cheng, Ya-Chin King, “An Ultra-Low Dark Current CMOS Image Sensor Using n+ Ring Reset”, IEEE Electron Device Letters, vol. 23, Sept. 2002:538-540
  3. Hsiu-Yu Cheng, Hsien-Chun Chang, Sing-Rong Li, Liang-Wei Lai, Ya-Chin King, “A New Photodiode Structure with Optical Window for High-Sensitivity CMOS Imagers”, Japanese Journal of Applied Physics, vol. 41, April 2002:2326-2328

2001

  1. Chou AHF, Yang ECS, Liu CJ, Pong HH, Liaw MC, Chao TS, King YC, Hwang HL, Hsu CCH, “Comprehensive study on a novel bidirectional tunneling program/erase NOR-type (BiNOR) flash memory cell” , IEEE Transactions on Electron Devices, July 2001 , vol. 48: (7): 1386-1393
  2. Ya-Chin King; Charles Kuo; Tsu-Jae King; Chenming Hu., “Optimization of sub-5nm multiple-thickness gate oxide formed by oxygen implantation”, IEEE Transactions on Electron Devices, Volume: 48, Issue: 6, June 2001: 1279 -1281
  3. Yen-Sun Wang, Tsai HP, Yang ECS, King YC, Chen S, Hsu CCH, “A Body-Effect-assisted NOR-type (BeNOR) multilevel flash memory”, Japanese Journal of Applied Physics, vol. 40, April 2001: 2954-2957
  4. Ya-Chin King; Tsu-Jae King; Chenming Hu., “Charge-trap memory device fabricated by oxidation of Si1-xGex”, IEEE Transactions on Electron Devices, Volume: 48, Issue: 4, April 2001: 696 -700
  5. Hai-Ming Lee; Cheg-Jye Liu; Chih-Wei Hsu; Mong-Song Liang; Ya-Chin King; Charles Hsu. “New Trap-Assisted Band-to-Band Tunneling Induced Gate Current Model for P-channel MOSFET with Sub-3nm Oxides”, Japanese Journal of Applied Physics, vol. 40, March 2001:1218-1221

2000

  1. Frank Lin; S.-Y. Lin; M.-L. Lee; C.-H. Boe; C.-P. Yeh; P.-H. Wu; N. J.; Ya-Chin King; Charles Hsu , “Novel source-controlled self-verified programming for multilevel EEPROMs “, IEEE Transactions on Electron Devices, Volume: 47 Issue: 6, June 2000: 1166 -1174
  2. -F. Chou; Wei-Zhe Wong; Jang, E.C.-S.; Yu-Yuan Yao; Ya-Chin King ; Charles Hsu.”Comprehensive study of a new self-convergent programming scheme for split gate flash memory.”, Japanese Journal of Applied Physics, April 2000, vol.39, (no.4B): 2219.
  3. -F. Chou; Yang, E.C.-S.; Wei-Zhe Wong; Ya-Chin King; Charles Hsu. “A new bit-line-controlled self-convergent multilevel AND-type flash memory. “, Japanese Journal of Applied Physics, April 2000, vol.39, (no.4B): 2215.

1999

  1. Ya-Chin King; Tsu-Jae King; Chenming Hu. “A long-refresh dynamic/quasi-nonvolatile memory device with 2-nm tunneling oxide.”IEEE Electron Device Letters, Aug. 1999, vol.20, (no.8): 409.
  2. Liu; X. Jin; Ya-Chin King; Chenming Hu.,“An efficient and accurate compact model for thin-oxide-MOSFET intrinsic capacitance considering the finite charge layer thickness.”, IEEE Transactions on Electron Devices, May 1999, vol.46, (no.5): 1070.
  3. Kevin Yang; Chenming Hu; and Ya-Chin King. “Oxide Thickness Characterization: Models for Quantum Effect,” Solid State Technology, Taiwan, no. 6, p. 51, 1999

1998

  1. Dunggun Park, Ya-Chin King, Qiang Lu, Tsu-Jae King, Chenming Hu, and Others. “Transistor Characteristics with Ta2O5 Gate Dielectric”, IEEE Electron Device Letters, November 1998, vol. 19, ( no. 11): 441
  2. Ya-Chin King; Hiroshi Fujioka; Shiroo Kamohara; Kai Chen; Chenming Hu.“DC Electrical Oxide Thickness Model for Quantization of the Inversion Layer in MOSFETs”, Semiconductor Science and Technology, August 1998, (no.13): 963
  3. Wen-Chin Lee; Ya-Chin King; Tsu-Jae King; Chenming Hu.”Observation of reduced poly-gate depletion effect for poly-Si0.8Ge0.2-gated NMOS devices.” Electrochemical and Solid-State Letters, July 1998, vol.1, (no.1): 58.
  4. Chenming Hu; Donggun Park; Ya-Chin King.”Thin Gate Oxides Promise High Reliability “, Semiconductor International, July 1998, p.215
  5. Wen-Chin Lee; Ya-Chin King; Tsu-Jae King ; Chenming Hu.”Investigation of Poly-Si1-xGex for Dual-Gate CMOS Technology”, IEEE Electron Device Letters, July 1998, vol.19, ( no. 7): 247.
  6. Ya-Chin King; Hiroshi Fujioka; Shiroo Kamohara ;Chenming Hu., “Small-signal electron charge centroid Model for quantization of Inversion Layer in a metal-on-insulator field-effect transistor”, Applied Physics Letters, June 1998, vol.72, (no. 26): 3476.

1996

  1. Ya-Chin King; Bin Yu; J. Pohlman; Chenming Hu.”Punchthrough diode as the transient voltage suppressor for low-voltage electronics.”, IEEE Transactions on Electron Devices, Nov. 1996, vol.43, (no.11): 2037.

1995

  1. Ya-Chin King; Bin Yu; J. Pohlman; Chenming Hu.”Punchthrough transient voltage suppressor for low-voltage electronics.”, IEEE Electron Device Letters, July 1995, vol.16, (no.7): 303.