{"id":25,"date":"2018-04-20T21:03:34","date_gmt":"2018-04-20T13:03:34","guid":{"rendered":"http:\/\/well.ee.nthu.edu.tw\/?page_id=25"},"modified":"2026-01-09T20:01:15","modified_gmt":"2026-01-09T12:01:15","slug":"%e6%9c%83%e8%ad%b0%e7%99%bc%e8%a1%a8","status":"publish","type":"page","link":"https:\/\/starlab.ee.nthu.edu.tw\/?page_id=25","title":{"rendered":"\u6703\u8b70\u767c\u8868"},"content":{"rendered":"\r\n

PUBLICATIONS (1995 \u2013 Dec 2025)<\/strong><\/p>\r\n

Conference Paper (154 papers)<\/strong><\/p>\r\n

2025<\/u><\/strong><\/p>\r\n

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  1. Wei-Hwa Lin, Pin-Hsuan Shih, Tzu-Ying, Sung, Yue-Der Chih, Yih Wang, Jonathan Chang, Ya-Chin King<\/strong><\/span>, Chrong Jung Lin<\/strong><\/span>, \u201cUltra High Density 1D1R FinFET Dielectric RRAM in 5nm FinFET CMOS Logic Process ,\u201d in 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco USA, Dec. 2025.<\/li>\r\n
  2. Wei Chang, Chieh-Hsin Lin, Ching-Hsing Fang, Tzu-Hao Yu, Ching-Yun Chang, Wun-Jie Lin, Jam-Wem Lee, Kuo-Ji Chen, Ming-Hsiang Song, Yue-Der Chih, Yih Wang, Jonathan Chang, Ya-Chin King<\/strong><\/span>, Chrong Jung Lin<\/strong><\/span>, \u201c5nm FinFET Differential Plasma Recorder Device\u201d in 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco USA, Dec. 2025.<\/li>\r\n
  3. Wei-Hwa Lin, Jian-Yu Wang, Yue-Der Chih, Yih Wang, Jonathan Chang, Ya-Chin King<\/strong><\/span>, Chrong Jung Lin<\/strong><\/span>, \u201cTrimmable Via Pin Array Capacitor in Fully Compatible CMOS Logic Process in 16nm FinFET Platform,\u201d in 2025 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2025.<\/li>\r\n
  4. Wei-Hwa Lin, Tsung-Pei Yang, Kai-Ching Chuang, Howard Tseng, Tassa Yang, Sung-Po Liao, Tim Chung, Ya-Chin King<\/strong><\/span>, Chrong Jung Lin<\/strong><\/span>, \u201cCharacterization and Modeling of 16nm FinFET 3D Stackable Via RRAM ,\u201d in 2025 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2025.<\/li>\r\n
  5. Fang-Yu Ye, Bing-Rong Tang , Chrong-Jung Lin<\/strong><\/span>, and Ya-Chin King<\/strong><\/span> \u201cBi-directional Read Scheme for HighDensity FinFET Based Multilevel OTP Memory ,\u201d in 2025 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2025.<\/li>\r\n
  6. Ho-Ting Chao, Shang-Chen Tsai, Wei-Chang, Burn-Jeng Lin, Jiaw-Ren Shih, Chrong-Jung Lin<\/strong><\/span>, and Ya-Chin King<\/strong><\/span> \u201cA Study of Electron Beam Focusing and Depth Profiling by DUV-Induced Surface Charging of Floating Metal Electrode Arrays\u201d in 2025 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2025.<\/li>\r\n
  7. Chieh-Hsin Lin, Wei Chang ,Wei-Hwa Lin, Ching-Yun Chang, Wun-Jie Lin, Jam-Wem Lee, Kuo-Ji Chen, Ming-Hsiang Song, Yue-Der Chih, Eric Wang, Jonathan Chang, Ya-Chin King<\/strong><\/span>, Chrong Jung Lin<\/span><\/strong>, \u201cHigh Resolution Well-Plasma Detection Device in 16nm CMOS FinFET Process,\u201d in 2025 IEEE Symposia on VLSI Technology and Circuits (IEEE Symp of VLSI), Japan. June. 2025.<\/li>\r\n
  8. Pin-Hsuan Shih, Wei-Hwa Lin, Yue-Der Chih, Eric Wang, Jonathan Chang, Ya-Chin King<\/strong><\/span>, Chrong Jung Lin<\/span><\/strong>, \u201cHigh Density 7nm FinFET Dielectric RRAM in Embedded Memory Applications,\u201din 2025 IEEE Symposia on VLSI Technology and Circuits (IEEE Symp of VLSI), Japan. June. 2025.<\/li>\r\n
  9. Ting Kan, Kai-Ching Chuang, Bing-Rong Tang, Jiaw-Ren Shih, Chrong-Jung Lin<\/span><\/strong> and Ya-Chin King<\/strong><\/span>, ” A Study of Bit Revival Operation for Logic Compatible Twin-bit RRAM in FinFET Technologies, ” 2025 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), HsinChu, Taiwan, Apr. 2025.<\/li>\r\n
  10. Hsin-Hung Yeh, Min-Hsun Chuang, Jiaw-Ren Shih, Chrong-Jung Lin<\/span><\/strong> and Ya-Chin King<\/strong><\/span>, \u201cLogic-Compatible Low-Voltage Complementary Analog Memory by CMOS FinFET Technology,\u201d 2025 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), HsinChu, Taiwan, Apr. 2025.<\/li>\r\n<\/ol>\r\n

    2024<\/u><\/strong><\/p>\r\n

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    1. Han-Lin Huang, Wei-Chang, Yu-Der Chih, Jonathan Chang, Chrong-Jung Lin<\/span><\/strong> and Ya-Chin King<\/strong><\/span>, \u201cOn-Wafer Polarity-Specific Response Plasma Charging Recorder with Fin-Coupling Structure by FinFET Technology,\u201d in 2024 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2024.<\/li>\r\n
    2. Wei-Hwa Lin, Ting-Kai Huang, Yue-Der Chih, Yih Wang, Jonathan Chang, Ya-Chin King<\/strong><\/span>, Chrong Jung Lin<\/span><\/strong>, \u201c1T EUV\/DUV Detector in Fully Compatible 16nm FinFET Logic Process,\u201d in 2024 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2024.<\/li>\r\n
    3. Ho-Ting Chao, Yu-Jie Teng, Chrong-Jung Lin<\/strong><\/span>, and Ya-Chin King<\/span><\/strong>, “A Study of E-beam Concentrating Effect in Detector Array with Pre-charged Electrodes”, in 2024 International Electron Devices & Materials Symposium (IEDMS), Taichung, Aug. 2024.<\/li>\r\n
    4. Fang-Yu Ye, Geng-Shiu Lin, Chrong-Jung Lin<\/span><\/strong> and Ya-Chin King<\/strong><\/span>, \u201cCharacterization of 2T One-Time Programmable Memory in 16nm and 28nm logic NVM Applications,\u201d in 2024 International Electron Devices & Materials Symposium (IEDMS), Taichung, Aug. 2024.<\/li>\r\n
    5. Li-Yu Wang, Kuan-Ju Chen, Perng-Fei Yuh, Yih Wang, Jonathan Chang, Ya-Chin King<\/strong><\/span>, and Chrong Jung Lin<\/strong><\/span>, “A New Ultra-Low Voltage Metal Fuse for High Density OTP Applications,”\u00a02024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)<\/em>, HsinChu, Taiwan, 2024<\/li>\r\n
    6. Geng-Shiu Lin, Ya-Chin King<\/strong><\/span> and Chrong-Jung Lin<\/strong><\/span>, “A Study of Physical Unclonable Function by Dielectric Breakdown in High-\u03ba Metal Gate Device,”\u00a02024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)<\/em>, HsinChu, Taiwan, 2024.<\/li>\r\n
    7. Ting-Kai Huang, Hsin-Hung Yeh, Jiaw-Ren Shih, Chrong-Jung Lin<\/strong><\/span>, and Ya-Chin King<\/strong><\/span>, “Complementary Detectors for DUV Sensing by CMOS Logic Technology,” 2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA)<\/em>, HsinChu, Taiwan, 2024.<\/li>\r\n<\/ol>\r\n

      2023<\/u><\/strong><\/p>\r\n

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      1. Li-Yu Yeh, Ya-Lin Chang, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin <\/u><\/strong>and\u00a0Ya-Chin King<\/u>*, <\/strong>“3D Stack Ultra High Resistance Via Matrix by Cu BEOL Structures in Nano-scaled CMOS Processing Node”, in 2023 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2023.<\/li>\r\n
      2. Yi-Han Huang, Kuan-Chung Chiu, Yu-Jie Teng, Burn Jeng Lin, Jiaw-Ren Shih, Faith Yuh, Eric Wang, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin <\/u><\/strong>and\u00a0Ya-Chin King<\/u>*, <\/strong>\u201cOn-Wafer 3D E-beam Detector Cube by FinFET CMOS Technologie\u201d, in 2023 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2023.<\/li>\r\n
      3. Yu-Cheng Lin, Yao-Hung Huang, Kai-Ching Chuang, Yu-Der Chih, Jonathan Chang,\u00a0Chrong Jung Lin <\/u><\/strong>and\u00a0Ya-Chin King<\/u>*<\/strong>, \u201cTwin-bit Via RRAM with Unique Diode State in Cross-bar Arrays by Advanced CMOS Cu BEOL Process,\u201d in 2023 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2023.<\/li>\r\n
      4. Che-Chuan Liu, Hsin-Yi Shen, Kuangye Wang, Yu\u2010Lun Chueh, Yue-Der Chih, Jonathen Chang, Jiaw-Ren Shih,\u00a0Chrong-Jung Lin<\/u><\/strong>,\u00a0Ya-Chin King<\/u>*<\/u><\/strong>, “Selenized 2D Film Based Gas Sensor with Self Convergent Calibration”, in 2023 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2023.<\/li>\r\n
      5. Yao-Hung Huang, Yu-Cheng Hsieh, Yu-Cheng Lin, Yue-Der Chih, Eric Wang, Jonathan Chang,\u00a0Ya-Chin King<\/u><\/strong>,\u00a0Chrong Jung Lin<\/u><\/strong>*, \u201cHigh Density Embedded 3D Stackable Via RRAM in Advanced MCU Applications,\u201d in 2023 IEEE Symposia on VLSI Technology and Circuits (IEEE Symp of VLSI), Kyoto, Japan, June 2023.<\/li>\r\n
      6. Wei-Hwa Lin, Jiaw-Ren Shih, Jonathan Chang, Yih Wang, Perng-Fei Yuh, Ya-Chin King<\/u><\/strong>, Chrong Jung Lin<\/u><\/strong>*, \u201c16nm FinFET DUV Detector Array in Fully Compatible FinFET Logic Process,\u201d in 2023 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Apr. 2023.<\/li>\r\n
      7. Li-Yu Yeh, Chrong-Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, “Offset-Via Anti-fuse by Cu BEOL Process in Advanced CMOS Technologies” in 2023 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Apr. 2023.<\/li>\r\n
      8. Gui-Sheng Chao, Wei-Hua Chen, Kuan-Ju Chen, Chrong-Jung Lin, Ya-Chin King<\/strong><\/span>, \u201cCharacterization and Current Modeling of Stacked high-\u03ba Metal-Insulator-Metal Capacitors\u201d in 2023 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Apr. 2023.<\/li>\r\n<\/ol>\r\n

        2022<\/u><\/strong><\/p>\r\n

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        1. Wei-Hwa Lin, Li Ci Chen, Ming-Han Ho, Hong-Shen Chen, Yu-Lun Hu, Burn Jeng Lin, Pin-Jiun Wu, Jenny Yi-Chun Liu, Yue-Der Chih, Jonathen Chang, Jiaw-Ren Shih, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, \u201cA New Self-Powered Wireless Sensing Circuitry for On-Wafer In-Situ EUV Detection,\u201d in 2022 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2022.<\/li>\r\n
        2. Chang-Pei Yeh, Geng-Shiu Lin,\u00a0Chrong Jung Lin<\/u>,\u00a0Ya-Chin King*<\/u><\/strong>, “High-k Metal Gate Complementary Cells in Physical Unclonable Function Array”,\u00a0in 2022 International Electron Devices & Materials Symposium (IEDMS), Nantou, Oct. 2022.<\/li>\r\n
        3. Li-Yu Yeh, Li-Yu Wang, Chrong Jung Lin<\/u>,\u00a0Ya-Chin King*<\/u><\/strong>, <\/u>“Low-Current Programming Offset-Via Fuse in FinFET Cu BEOL Process”,\u00a0in 2022 International Electron Devices & Materials Symposium (IEDMS), Nantou, Oct. 2022.<\/li>\r\n
        4. I-Hsin Yang, Li-Yu Yeh, Chrong Jung Lin <\/u><\/strong>and Ya-Chin King*<\/u><\/strong>, “Current-Divider-Via Assisted Metal-Fuse OTP Memory in FinFET CMOS Technologies,” in 2022 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2022.<\/li>\r\n
        5. Wei-Hua Chen, Gui-Sheng Chao,\u00a0Chrong Jung Lin <\/u><\/strong>and Ya-Chin King*<\/u><\/strong>, \u201cReliability Study of Stacked high-\ud835\udf3f Metal-Insulator-Metal Capacitors,\u201d\u00a0in 2022 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2022.<\/li>\r\n
        6. Hsin-Yuan Yu, Yao-Hung Huang, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin <\/u><\/strong>and Ya-Chin King*<\/u><\/strong>, \u201cPure CMOS embedded Artificial Synaptic Device (eASD) for High Density Neuromorphic Computing Chip,\u201d in 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Apr. 2022.<\/li>\r\n
        7. Wei-Hwa Lin, Chien-Ping Wang, Jiaw-Ren Shih, Chrong-Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, \u201c2T-Pixel Sensors Array for on-Wafer in-Chamber DUV Sensing,\u201d in 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Apr. 2022.<\/li>\r\n
        8. Wang-Yi Lee, Chang-Pei Yeh, Ya-Chin King <\/u><\/strong>and Chrong Jung Lin*<\/u><\/strong>, \u201cSelf-Inhibit Complementary Cells by High-k Metal Gate Transistors for Physical Unclonable Function,\u201d in 2022 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Apr. 2022.<\/li>\r\n
        9. Kai-Wei Yang, Yi-Jei Chao, Jiaw-Ren Shih, Chrong-Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, \u201cAn Investigation of Plasma Charging Effect on FinFET Front-End-of-Line Processes,\u201d in 2022 IEEE Electron Devices Technology and Manufacturing (EDTM), Oita, Mar. 2022.<\/li>\r\n<\/ol>\r\n

          2021<\/u><\/strong><\/p>\r\n

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          1. Wei Chang, Yi-Jie Chao, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, \u201cPhysical Unclonable Function by Random Plasma Charging Event in FinFET CMOS Processes,\u201d in 2021 International Electron Devices & Materials Symposium (IEDMS), Tainan, Nov. 2021.<\/li>\r\n
          2. Chia-Ru Lu, Chien-Ping Wang, Jiaw-Ren Shih, Chrong Jung Lin <\/u><\/strong>and Ya-Chin King*<\/u><\/strong>, \u201cOn-Wafer DUV Detector Through Metal Sensing Pad by 28nm CMOS Technologies,\u201d in 2021 International Electron Devices & Materials Symposium (IEDMS), Tainan, Nov. 2021.<\/li>\r\n
          3. Wei-Cheng Zhuang, Wei-Hwa Lin, Chrong-Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, \u201cFinFET-based P-channel Logic Compatible Differential Floating Gate Memory Cells by Cross-coupled Structure,\u201d in 2021 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2021.<\/li>\r\n
          4. Yao-Hung Huang, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, \u201cOperation Optimization of Logic Compatible 2T RRAM Array by High-\u03ba Metal Gate CMOS Logic Technologies\u201d in 2021 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2021.<\/li>\r\n
          5. Chien-Ping Wang, Burn Jeng Lin, Jiaw-Ren Shih, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, \u201cOn-Wafer Electronic Layer Detectors Array (ELDA) for e-beam Imaging in Advanced Lithographic Systems,\u201d in 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Apr. 2021.<\/li>\r\n
          6. Che-Wei Chu, Chrong Jung Lin<\/u><\/strong>, Ya-Chin King*<\/u><\/strong> and Wei-Hua Chen, \u201cA Twin Bit AND-Type Multiple-Time-Programming Memory Cell by Nano-scaled High\u2013k Metal Gate Process,\u201d in 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Apr. 2021.<\/li>\r\n<\/ol>\r\n

            2020<\/u><\/strong><\/p>\r\n

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            1. Wei-Cheng Zhuang, Ching-Ting Chien, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, \u201cPulse Clamping for Threshold Voltage Control in Embedded Non-volatile Multiple-Level Memory Cell,\u201d in 2020 International Electron Devices & Materials Symposium (IEDMS), Taoyuan, Oct. 2020.<\/li>\r\n
            2. Chih-An Yang, Shi Jiun Wang, Burn Jeng Lin, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, “On-Wafer Electron Beam Detectors by Floating-Gate FinFET Technologies,” in 2020 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2020.<\/li>\r\n
            3. Chi Su, Yi-Jie Chao, Chrong-Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, “On-Wafer Recorders for Assessing Wide Range Plasma Induced Charging Effect in FinFET Processes,” in 2020 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2020.<\/li>\r\n
            4. Chun-Yu Chuang, Chrong-Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, “Sidewall Erased Multiple-Time Programmable Memory Cells in FinFET Technologies,” in 2020 International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2020.<\/li>\r\n
            5. Chien-Ping Wang, Ying-Chun Shen, Kun-Lin Liou, Yu-Lun Chueh, Yue-Der Chih, Jonathan Chang, Jiaw-Ren Shih, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, \u201cHair-Like Nanostructure Based Ion Detector by 16nm FinFET Technology,\u201d in 2020 IEEE Symposia on VLSI Technology and Circuits (VLSI), Honolulu, HI, June 2020.<\/li>\r\n
            6. Cheng-Jun Lin, Chrong-Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, \u201c3D Stackable Via RRAM Cells by Cu BEOL Process in FinFET CMOS Technologies,\u201d in 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Aug. 2020.<\/li>\r\n
            7. Fu-Cheng Chang, Yao-Hung Huang, Chrong-Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, \u201cA Study of Read Variability in Backfill Contact Random Access Memory,\u201d in 2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Aug. 2020.<\/li>\r\n<\/ol>\r\n

              2019<\/u><\/strong><\/p>\r\n

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              1. Chieh Lee, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King*,<\/u><\/strong>\u201cMemory-Logic Hybrid Gate with 3D-Stackable Complementary Latches for FinFET-based Neural Networks,\u201d in 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2019.<\/li>\r\n
              2. Chi Su*, Yi-Pei Tsai, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King,<\/u><\/strong> \u201cPlasma Induced Damage on Inter-Metal Dielectric in Nano-meter FinFET Processes,\u201d in 2019 International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, Sept. 2019.<\/li>\r\n
              3. Yu-Fan Chiang, Che-Wei Chu*, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King,<\/u><\/strong> \u201cCross-Coupled Differential Multiple-Time-Programming Memory Cells by CMOS FinFET Technologies,\u201d in 2019 International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, Sept. 2019<\/li>\r\n
              4. Ching-Ting Chien, Chun-Yu Chuang*, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King<\/u><\/strong>, \u201cMulti-level Operations by Self-clamping Programming Scheme on Fine Floating Gate MTP Cells,\u201d in 2019 International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, Sept. 2019<\/li>\r\n
              5. Yun-Feng Kao, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, \u201cStochastic Filament Formation on the Cycling Endurance of Backfilled Contact Resistive Random Access Memory Cells,\u201d 2019 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Apr. 2019.<\/li>\r\n
              6. Chieh Lee, Yu-Ting Hung, Cheng-Jun Lin, Ya-Chin King<\/u><\/strong>, and Chrong Jung Lin*<\/u><\/strong>, \u201cTwin-Bit Resistive Random Access Memory in FinFET CMOS Logic Technologies,\u201d 2019 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Apr. 2019.<\/li>\r\n<\/ol>\r\n

                2018<\/u><\/strong><\/p>\r\n

                  \r\n
                1. Yi-Pei Tsai, Jiaw-Ren Shih, Ya-Chin King<\/u><\/strong> and Chrong Jung Lin*<\/u><\/strong>, \u201c7nm FinFET Plasma Charge Recording Device,\u201d in 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2018.<\/li>\r\n
                2. Peng-Chun Liou, Tsung-Han Lee, Chien-Ping Wang, Yu-Lun Chueh, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin<\/u><\/strong>, Ya-Chin King*<\/u><\/strong>, \u201cHigh Resolution Ion Detector (HRID) by 16nm FinFET CMOS Technology,\u201d in 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2018.<\/li>\r\n
                3. Yu-hung Yeh, Ching-Timg Chien*, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King<\/u><\/strong>, \u201cEmbedded Multiple-Time Programmable Memory by BCD Process for High voltage Circuits,\u201d in 2018 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sept. 2018<\/li>\r\n
                4. Wei-Hao Chen, Kai-Xiang Li, Wei-Yu Lin, Kuo-Hsiang Hsu, Pin-Yi Li, Cheng-Han Yang, Cheng-Xin Xue, En-Yu Yang, Yen-Kai Chen, Yun-Sheng Chang, Tzu-Hsiang Hsu, Ya-Chin King<\/u><\/strong>, Chorng-Jung Lin<\/u><\/strong>, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang, \u201cA 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors,\u201d in 2018 IEEE International Solid – State Circuits Conference – (ISSCC), San Francisco, CA, April 2018, pp. 494-496.<\/li>\r\n
                5. Jen Chieh Kuo, Ya-Chin King*<\/u><\/strong> and Chrong-Jung Lin<\/u><\/strong>, \u201cTemperature Effect on Operations and Characteristics of p-channel FinFET Dielectric RRAM,\u201d in 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, April 2018, pp. 1-2.<\/li>\r\n
                6. Chih-Yuan Chen, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King*,<\/u><\/strong> \u201cTemperature and Stress Effect of Random Telegraph Noise in FIND RRAM Arrays,\u201d in 2018 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, April 2018, pp. 1-2.<\/li>\r\n
                7. Zih-Hong Chen, Chien-Ping Wang, Po-Hsiang Huang, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King*,<\/u><\/strong> \u201cEmbedded Tunable Near Infrared Sensor with Programmable Potential Barrier on Nano-meter CMOS Platforms,\u201d in 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM), Kobe, Mar. 2018, pp. 274-276.<\/li>\r\n<\/ol>\r\n

                  2017<\/u><\/strong><\/p>\r\n

                    \r\n
                  1. Wei-Yu Chien, Tai-Min Wang, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin<\/u><\/strong>, and Ya-Chin King*<\/u><\/strong>, \u201cTwin Mode NV Logic Gates for High Speed Computing System on 16nm FINFET CMOS Logic Process,\u201d in 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2017, pp. 12.1.1-12.1.4.<\/li>\r\n
                  2. Peng-Chun Liou, Bo-Rong Huang, Chrong-Jung Lin<\/u><\/strong> and Ya-Chin King<\/u><\/strong>, \u201cAtto-Farad Capacitance Measurement for FinFETs by Vertical Fin Coupling Structure,\u201d in 2017 International Electron Devices & Materials Symposium (IEDMS), Hsinchu, Sep. 2017.<\/li>\r\n
                  3. Zih-Hong Chen, Yu-hung Yeh, Po-Ruei Cheng, Chrong Jung Lin<\/u><\/strong>, Ya-Chin King<\/u><\/strong>, \u201cAn Investigation of Light Triggering Effect on the Programming of Gate-less Anti-Fuse Cells,\u201d in 2017 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, Sept. 2017<\/li>\r\n
                  4. Yi-Hong Shih, Meng-Yin Hsu, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King<\/u><\/strong>, \u201cTwin-bit Via RRAM in 16nm FinFET Logic Technologies,\u201d in 2017 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, Sept. 2017<\/li>\r\n
                  5. Wei-Ting Hsieh, Yue-Der Chih, Jonathan Chang, Chrong-Jung Lin<\/u><\/strong> and Ya-Chin King<\/u><\/strong>, \u201cDifferential Contact RRAM Pair for Advanced CMOS Logic NVM applications,\u201d in 2017 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, Sep. 2017<\/li>\r\n
                  6. Tai-Min Wang, Wei-Yu Chien, Chia-LingHsu, Yue-Der Chih, Chrong Jung Lin<\/u><\/strong>, and Ya-Chin King*<\/u><\/strong>, \u201cP-channel Differential Multiple-Time Programmable Memory Cells by Laterally Coupled Floating Metal Gate FinFETs,\u201d in 2017 International Conference on Solid State Devices and Materials (SSDM), Sendai, Japan, Sep. 2017<\/li>\r\n
                  7. Chieh-Pu Lo, Wen-Zhang Lin, Wei-Yu Lin, Huan-Ting Lin, Tzu-Hsien Yang, Yen-Ning Chiang, Ya-Chin King<\/u><\/strong>, Chrong-Jung Lin<\/u><\/strong>, Yu-Der Chih, Tsung-Yung Jonathon Chang, Mon-Shu Ho and Meng-Fan Chang*, \u201cEmbedded 2Mb ReRAM macro with 2.6ns read access time using dynamic-trip-point-mismatch sampling current-mode sense amplifier for IoE applications,\u201d in 2017 Symposium on VLSI Circuits, Kyoto (VLSI), 2017, pp. C164-C165.<\/li>\r\n
                  8. Yu-Hung Yeh, Sheng-Hung Shih, Jen-Chien Fu, Chrong-Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, \u201cAn Investigation of Program Disturb Characteristics and Data Pattern Effect in 128G 3D NAND Flash Memories,\u201d in 2017\u00a0International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, 23 Apr. 2017<\/li>\r\n
                  9. Yi-Hung Chang, Po Shao Yeh, Yue-Der Chih, Jonathan Chang, Ya-Chin King<\/u><\/strong> and Chrong Jung Lin*<\/u><\/strong>, \u201c3D Time-Contingent Physical Unclonable Function Array on 16nm FinFET Dielectric RRAM,\u201d in 2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Toyama, Japan, Mar. 2017.<\/li>\r\n
                  10. Ting-Huan Hsieh, Yi-Pei Tsai, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, \u201cCharge Splitting In-situ Recorder (CSIR) for Monitoring Plasma Damage in FinFET BEOL Processes,\u201d in 2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Toyama, Japan, Mar. 2017.<\/li>\r\n<\/ol>\r\n

                    2016<\/u><\/strong><\/p>\r\n

                      \r\n
                    1. Jo En Yuan, Jen Chieh Kuo, Yu-Zheng Chen, Chrong Jung Lin<\/u><\/strong>, Ya-Chin King<\/u><\/strong> , \u201cAn Investigation of P-channel One-Time-Programming Cells by High-\u03ba Metal Gate CMOS Logic Process\u201d in 2016 International Electron Devices & Materials Symposium (IEDMS), Nov. 2016.<\/li>\r\n
                    2. Chieh-Pu Lo, Wei-Hao Chen, Zhibo Wang, Albert Lee, Kuo-Hsiang Hsu, Ya-Chin King<\/u><\/strong>, Chrong Jung Lin<\/u><\/strong>, Yongpan Liu, Huazhong Yang, Pedram Khalili, Kang-Lung Wang, and Meng-Fan Chang*, “A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era,” 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2016, pp. 16.3.1-16.3.4.<\/li>\r\n
                    3. Chu-Feng Liao, Meng-Yin Hsu, Yu-Der\u00a0Chih, Ya-Chin King*<\/u><\/strong>, and Chrong Jung Lin<\/u><\/strong>, \u201cZero Static-Power 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process,\u201d 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2016.<\/li>\r\n
                    4. Chia-Ling Hsu, Chu-Feng Liao, Wei-Yu Chien, Yue-Der Chih, Chrong Jung Lin<\/u><\/strong>, and Ya-Chin King<\/u><\/strong>, “Differential Multiple-Time-Programming Memory Cells by Laterally Coupled Floating Metal Gate FinFETs,” 2016 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, 29 Sep. 2016.<\/li>\r\n
                    5. Bo-Rong Huang, Fan-Hsuan Meng, Ya-Chin King<\/u><\/strong> and Chrong Jung Lin<\/u><\/strong>, “An Investigation of the Parasitic RC Effects in Nano-scaled FinFETs and Its Impact on SRAM Cells,” 2016 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, 29 Sep. 2016.<\/li>\r\n
                    6. Yun Feng Kao, Wei Ting Hsieh, Chun Che Chen, Ya-Chin King<\/u><\/strong>, and Chrong Jung Lin<\/u><\/strong>, “Statistical Analysis of the Correlations between Cell Performance and its Initial States in CRRAM Cells,” 2016 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, 27 Sep. 2016.<\/li>\r\n
                    7. Hsien Hao Chen, Sheng-Hung Shih, Ya-Chin King<\/u><\/strong>, and Chrong Jung Lin,<\/u><\/strong> \u201cDesign and characterization of Logic Compatable Drain Extended FinFETs for Embedded High-Voltage Circuits,\u201d 2016 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, Sep. 2016.<\/li>\r\n
                    8. Meng-Yin Hsu, Yu-Der\u00a0Chih, Ya-Chin King<\/u><\/strong>, and Chrong Jung Lin<\/u><\/strong>, \u201cGate Contact RRAM in Nano-scaled FinFET Logic Technologies,\u201d 2016 International Conference on Solid State Devices and Materials (SSDM), Tsukuba, 27 Sep. 2016.<\/li>\r\n
                    9. Mingte Lin, Chihching Yang, Hung-Yu Chen, Alex Juan, K. C. Su and Ya-Chin King<\/u><\/strong> “Evaluation of inter and intra level TDDB of Cu\/Low-k interconnect for high voltage application,” 2016 IEEE International Reliability Physics Symposium (IRPS), Pasadena, CA, 2016, pp. DI-6-1-DI-6-4.<\/li>\r\n
                    10. Hung-Yu Chen, Hsien-Hao Chen, Yun-Feng Kao, Ping-Yu Chen, Ya-Chin King<\/u><\/strong>, Chrong Jung Lin*<\/u><\/strong>, “A new manufacturing method of CMOS logic compatible 1T-CRRAM,” 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, 2016, pp. 1-2.<\/li>\r\n
                    11. Po-Ruei Cheng, Chih-Sung Yang, Meng-Yin Hsu, Chrong Jung Lin<\/u><\/strong>, Ya-Chin King*<\/u><\/strong> , “Variable-length gateless transistor for analog one-time-programmable memory applications,” 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, 2016, pp. 1-2.<\/li>\r\n<\/ol>\r\n

                      2015<\/u><\/strong><\/p>\r\n

                        \r\n
                      1. Chun-Hsiung Wu, Yi-Pei Tsai, Chrong Jung Lin<\/u><\/strong>, Ya-Chin King*<\/u><\/strong>, “Mapping of Wafer-Level Plasma Induced Charge Contour by Novel On-chip In-Situ Recorders in Advance FinFET Technologies,\u201d in 2015 IEEE International Electron Devices Meeting (IEDM), Washington, D.C., 7-9 Dec. 2015.<\/li>\r\n
                      2. Hsin Wei Pan, Kai Ping Huang, Shih Yu Chen, Ping Chun Peng, Zhi Sung Yang, Cheng-Hsiung Kuo, Yue-Der Chih, Ya-Chin King<\/u><\/strong> and Chrong Jung Lin*<\/u><\/strong>, ” 1Kbit FINFET Dielectric (FIND) RRAM in Pure 16nm FinFET CMOS Logic Process,\u201d in 2015 IEEE International Electron Devices Meeting (IEDM), Washington, D.C., 7-9 Dec. 2015.<\/li>\r\n
                      3. Ping Chun Peng, Yu-Zheng Chen, Hsin Wei Pan, Woan Yun Hsiao, Kuang-Hsin Chen, Yu-Hsuan Kuo, Ching-Pin Lin, Bor-Zen Tien, Tzong-Sheng Chang, Ya-Chin King*<\/u><\/strong>, and Chrong Jung Lin<\/u><\/strong>, “A New High Density FinFET OTP Technology,\u201d in 2015 International Conference on Solid State Devices and Materials (SSDM), Sapporo, 30 Sep. 2015.<\/li>\r\n
                      4. Po-Yen Lin, Yu-Lun Chiu, Fan-Hsuan Meng, Kuang-Hsin Chen, Serena Hao, Bor-Zen Tien, Tzong-Sheng Chang, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, “Effect of 3D Current Distribution on Characterizing Parasitic Resistance of FinFETs,\u201d in 2015 International Conference on Solid State Devices and Materials (SSDM), Sapporo, 27 Sep. 2015.<\/li>\r\n
                      5. Yu-Wen Chung; Wen Chao Shen; Ping-Yu Chen; Zih-Song Wang; Huei-Haurng Chen; Ming-Jinn Tsai; Ya-Chin King<\/u><\/strong>; Chrong Jung Lin*<\/u><\/strong>, “A new ultra high density 1F1R MLC flash contact RRAM,” in VLSI Technology, Systems and Application (VLSI-TSA), 2015 International Symposium on., pp.1-2, 27-29 April 2015.<\/li>\r\n
                      6. Liang-Shun Chang; Yi-Che Yen; Kuei-Hung Shen; Ming-Jinn Tsai; Chrong Jung Lin<\/u><\/strong>; Ya-Chin King*<\/u><\/strong>, “Multi-channel magnetic transmission interface for 3D contactless connection,” in VLSI Technology, Systems and Application (VLSI-TSA), 2015 International Symposium on , pp.1-2, 27-29 April 2015.<\/li>\r\n<\/ol>\r\n

                        2014<\/u><\/strong><\/p>\r\n

                          \r\n
                        1. Yung-Wen Chin; Shu-En Chen; Min-Che Hsieh; Tzong-Sheng Chang; Chrong Jung Lin<\/u><\/strong>; Ya-Chin King*<\/u><\/strong>, “Point twin-bit RRAM in 3D interweaved cross-point array by Cu BEOL process,” in 2014 IEEE International Electron Devices Meeting (IEDM), San Francisco, 2014.<\/li>\r\n
                        2. Yuh-Te Sung; Po-Yen Lin; Jim Chen; Tzong-Sheng Chang; Ya-Chin King<\/u><\/strong>; Chrong Jung Lin*<\/u><\/strong>, “A new saw-like self-recovery of interface states in nitride-based memory cell,” in 2014 IEEE International Electron Devices Meeting (IEDM), San Francisco, Dec. 2014.<\/li>\r\n
                        3. Sheng-Yen Chien; Po Yen Lin; Hung-Yu Chen; Chrong Jung Lin<\/u><\/strong>; Ya-Chin King*<\/u><\/strong>, “Self-convergent trimming of embedded logic compatible OTP memory for VT variation reduction in low voltage SRAMs,” in VLSI Technology, Systems and Application (VLSI-TSA), Proceedings of Technical Program – 2014 International Symposium on , pp.1-2, 28-30 April 2014.<\/li>\r\n
                        4. Woan Yun Hsiao; Chin Yu Mei; Wen Chao Shen; Tzong Sheng Chang; Yue Der Chih; Ya-Chin King<\/u><\/strong>; Chrong Jung Lin*<\/u><\/strong>, “A high density Twin-Gate OTP cell in pure 28nm CMOS process,” in VLSI Technology, Systems and Application (VLSI-TSA), Proceedings of Technical Program – 2014 International Symposium on , pp.1-2, 28-30 April 2014.<\/li>\r\n<\/ol>\r\n

                          2013<\/u><\/strong><\/p>\r\n

                            \r\n
                          1. Min-Che Hsieh, Yu-Cheng Liao, Yung-Wen Chin, Chen-Hsin Lien, Tzong-Sheng Chang, Yue-Der Chih, Sreedhar Natarajan, Ming-Jinn Tsai, Ya-Chin King<\/u><\/strong>, and Chrong Jung Lin*<\/u><\/strong>, \u201cUltra High Density 3D Via RRAM in Pure 28nm CMOS Process\u201d, International Electron Devices Meeting (IEDM), New York, 2013.<\/li>\r\n
                          2. Ching-Hua Wang, Kun-Yu Dai, Kuei-Hung Shen,Yung-Hung Wang, and Ming-Jinn Tsai, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King*<\/u><\/strong>, \u201cMagnetic Wireless Interlayer Transmission through Perpendicular MTJ for 3D-IC Applications\u201d, International Electron Devices Meeting (IEDM), New York, 2013.<\/li>\r\n<\/ol>\r\n

                            2012<\/u><\/strong><\/p>\r\n

                              \r\n
                            1. Wen Chao Shen , Chin Yu Mei, Y. -D. Chih, Shyh-Shyuan Sheu, Ming-Jinn Tsai, Ya-Chin King<\/u><\/strong>, Chrong Jung Lin<\/u><\/strong>, \u201cHigh-K Metal Gate Contact RRAM (CRRAM) in Pure 28nm CMOS Logic Process,\u201d 2012 International Electron Devices Meeting (IEDM), San Francisco, Dec. 2012.<\/li>\r\n
                            2. Wang, K. Y. Tai1, L. C. Wang, C. Lin, C. H. Huang, J. Lin<\/u><\/strong>, and Y. C. King<\/u><\/strong>, \u201cSuper Junction Power MOSFET by Multi-step Trench Process,\u201d 2012 International Conference on Solid State Devices and Materials (SSDM), Kyoto, 2012.<\/li>\r\n
                            3. Tsao-Hsin Yang, Una Liauh, Y.-D. Chih, Chrong Jung Lin<\/u><\/strong>, Ya-Chin King<\/u><\/strong>, \u201cSingle Contact RRAM in Pure 65nm CMOS Logic Process,\u201d 2012 International Conference on Solid State Devices and Materials (SSDM), Kyoto, 2012.<\/li>\r\n
                            4. Chang, C. W. CW, C. C. Kuo, S. J. Shen, S. M. Yang, K. F. Lin, C. King<\/u><\/strong>, C. J. Lin<\/u><\/strong>, and Y. D. Chih, \u201cA 0.5V 4Mb Logic-Process Compatible Embedded Resistive RAM (ReRAM) in 65nm CMOS Using Low Voltage Current-Mode Sensing Scheme with 45ns Random Read Time\u201d 2012 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2012.<\/li>\r\n<\/ol>\r\n

                              2011<\/u><\/strong><\/p>\r\n

                                \r\n
                              1. Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Ya-Chin King<\/u><\/strong>, Chrong Jung Lin<\/u><\/strong>, Hung-Jen Liao, Yu-Der Chih, and Hiroyuki Yamauchi, \u201cAn Offset-Tolerant Current-Sampling-Based Sense Amplifier for Sub-100nA-Cell-Current Nonvolatile Memory\u201d, 2011 IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2011.<\/li>\r\n<\/ol>\r\n

                                2010<\/u><\/strong><\/p>\r\n

                                  \r\n
                                1. Ching-Hua Wang, Yi-Hung Tsai, Kai-Chun Lin, Meng-Fan Chang, Ya-Chin King<\/u><\/strong>, and Chrong Jung Lin<\/u><\/strong>, Shyh-Shyuan Sheu, Yu-Sheng Chen, Heng-Yuan Lee, Frederick T. Chen, and Ming-Jinn Tsai, \u201cThree-Dimensional 4F(2) ReRAM Cell with CMOS Logic Compatible Process\u201d, 2010 International Electron Devices Meeting (IEDM), Dec. 2010.<\/li>\r\n
                                2. Yuan Heng Tseng;Wen Chao Shen;Chia-En Huang;C. -H. Kuo;Y. -D. Chih;Chrong Jung Lin<\/u><\/strong>;Ya-Chin King<\/u><\/strong>, \u201cElectron Trapping Effect on the Switching Behavior of Contact RRAM Devices through Random Telegraph Noise Analysis\u201d, 2010 International Electron Devices Meeting (IEDM), Dec. 2010.<\/li>\r\n<\/ol>\r\n

                                  2009<\/u><\/strong><\/p>\r\n

                                    \r\n
                                  1. Te-Yu Lee, Chih-Chieh Chiu, Chrong Jung Lin<\/u><\/strong> and Ya-Chin King<\/u><\/strong>, \u201cHigh-Uniformity 2T1C AMOLED Panels by Using a New Built-In Trimming Method\u201d, 2009 International Symp. of the Society for Information Display (SID).<\/li>\r\n
                                  2. Yuan Heng Tseng, Chia-En Huang, C. -H. Kuo, Y. -D. Chih, Chrong Jung Lin<\/u><\/strong>, \u201cHigh Density and Ultra Small Cell Size of Contact ReRAM (CR-RAM) in 90nm CMOS Logic Technology and Circuits\u201d, 2009 IEEE International Electron Devices Meeting (IEDM), 2009.<\/li>\r\n
                                  3. Tzu-Hsuan Hsu, Hang-Ting Lue, Sheng-Chih Lai, Ya-Chin King<\/u><\/strong>, Kuang-Yeu Hsieh, Rich Liu, and Chih-Yuan Lu, \u201cReliability of planar and FinFET SONOS devices for NAND flash applications – Field enhancement vs. barrier engineering\u201d, VLSI Technology, Systems, and Applications (VLSI-TSA), Hsinchu, 2009, pp. 154-155.<\/li>\r\n<\/ol>\r\n

                                    2008<\/u><\/strong><\/p>\r\n

                                      \r\n
                                    1. Dai,\u00a0 J. Lin<\/u><\/strong>,\u00a0Y. C. King<\/u><\/strong>et al., “Low voltage transient voltage suppressor with v-groove structurec,” 2008 IEEE International Reliability Physics Symposium Proceedings – 46th Annual, International Reliability Physics Symposium, pp. 278-282, New York: IEEE, Electron Devices Soc & Reliability Group, 2008.<\/li>\r\n
                                    2. Hsu, H. T. Lue, W. C. Peng, C. H. Tsai, C. King<\/u><\/strong>, S. Y. Wang, M. T. Wu, S. P. Hong, J. Y. Hsieh, L. W. Yang, N. T. Lian, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, C. Y. Lu, A study of sub-40nm FinFET BE-SONOS NAND flash, New York: IEEE, 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, Proceedings<\/li>\r\n
                                    3. Hsu, H. T. Lue, W. C. Peng, C. King<\/u><\/strong>, C. W. Wu, S. Y. Wang, M. T. Wu, S. P. Hong, J. Y. Hsieh, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, C. Y. Lu, High performance and scalable FinFET BE-SONOS device for NAND Flash memory application, New York: IEEE, 2008 International Symposium on Vlsi Technology, Systems and Applications<\/li>\r\n<\/ol>\r\n

                                      2007<\/u><\/strong><\/p>\r\n

                                        \r\n
                                      1. Tsai, H. M. Chen, H. Y. Chiu, H. S. Shih, H. C. Lai, C. King<\/u><\/strong>, C. J. Lin<\/u><\/strong>, “45nm gateless anti-fuse cell with CMOS fully compatible process,” 2007 IEEE International Electron Devices Meeting, Vols 1 and 2, International Electron Devices Meeting, pp. 95-98, New York: IEEE, 2007.<\/li>\r\n
                                      2. Liang, S. I. Hsieh, H. T. Chen, J. Lin<\/u><\/strong>, Y. C. King<\/u><\/strong>, “Degradation dependent on channel width in sequential lateral solidified poly-Si thin film transistors,” 2007 IEEE International Reliability Physics Symposium Proceedings – 45th Annual, International Reliability Physics Symposium, pp. 682-683, New York: IEEE, 2007.<\/li>\r\n
                                      3. Huang, H. M. Chen, H. C. Lai, Y. J. Chen, C. King<\/u><\/strong>, C. J. Lin<\/u><\/strong>, “A new self-aligned nitride MTP cell with 45nm CMOS fully compatible process,” 2007 IEEE International Electron Devices Meeting, Vols 1 and 2, International Electron Devices Meeting, pp. 91-94, New York: IEEE, 2007.<\/li>\r\n
                                      4. Huang, H. M. Chen, M. B. Chen, C. King<\/u><\/strong>, C. J. Lin<\/u><\/strong>, A new CMOS logic anti-fuse cell with programmable contact, New York: IEEE, 2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop, New York: IEEE, 2007.<\/li>\r\n
                                      5. Hisu, H. T. Lue, E. K. Lai, J. Y. Hsieh, S. Y. Wang, L. W. Yang, C. King<\/u><\/strong>, T. Yang, K. C. Chen, K. Y. Hsieh, R. Liu, C. Y. Lu, “A high-speed BE-SONOS NAND Flash utilizing the field-enhancement effect of FinFET,” 2007 IEEE International Electron Devices Meeting, Vols 1 and 2, International Electron Devices Meeting, pp. 913-916, New York: IEEE, 2007.<\/li>\r\n
                                      6. Dai, H. N. Wang, M. T. Chiang, J. Lin<\/u><\/strong>, Y. C. King<\/u><\/strong>, “Leakage suppression of low voltage transient voltage suppressor,” 2007 IEEE International Reliability Physics Symposium Proceedings – 45th Annual, International Reliability Physics Symposium, pp. 592-593, New York: IEEE, 2007.<\/li>\r\n
                                      7. Cho, C. T. Peng, W. J. Chiang, J. Lin<\/u><\/strong>, C. W. Chao, K. C. Lin, Y. C. King<\/u><\/strong>, C. S. Weng, F. Y. Gan, Integrated ambient light sensor in LTPS LCD panel with silicon nanocrystals photosensor, Minato-Ku: Inst Image Information & Television Engineers, Idw ’07: Proceedings of the 14th International Display Workshops, Vols 1-3, 2007.<\/li>\r\n
                                      8. Chiang, C. Y. Chen, J. Lin<\/u><\/strong>, Y. C. King<\/u><\/strong>, A. T. Cho, C. T. Peng, C. W. Chao, K. C. Lin, F. Y. Gan, “Late-news poster: Silicon nanocrystals photo sensor integrated on low-temperature polycrystalline-silicon panels,” 2007 Sid International Symposium, Digest of Technical Papers, Vol Xxxviii, Books I and Ii, Sid International Symposium Digest of Technical Papers, pp. 294-297, Playa Del Rey: Soc Information Display, 2007 Sid International Symposium, Digest of Technical Papers, Vol Xxxviii, Books I and Ii<\/li>\r\n<\/ol>\r\n

                                        2006<\/u><\/strong><\/p>\r\n

                                          \r\n
                                        1. Chiang, H. C. Chen and\u00a0 C. King<\/u><\/strong>\u201cPhotodiode Model for CMOS Image Sensor SPICE Simulation\u201d, International Conference on Solid State Devices and Materials, Tokyo, Japan, September 2006<\/li>\r\n<\/ol>\r\n

                                          2005<\/u><\/strong><\/p>\r\n

                                            \r\n
                                          1. Chen HT, Hsieh SI, Chen YC, Tsai PH, Chen CL, Huang CJ, Lin JX, Chang CJ,\u00a0King YC<\/u><\/strong>. “Novel flash memory structure using sequential lateral solidified low temperature poly-Si technology”. IDW\/AD’05 – Proceedings of the 12th International Display Workshops in Conjunction with Asia Display 2005; 2005; Takamatsu, Japan<\/li>\r\n
                                          2. Wu M-Y, Feng S-C,\u00a0King Y-C<\/u><\/strong>. “A novel single poly-silicon EEROM using trench floating gate”. Records of the IEEE International Workshop on Memory Technology, Design and Testing; 2005; Taipei, Taiwan<\/li>\r\n
                                          3. Hu L-C, Kang A-C, Wu TI, Chen E, Shih JR, Chin HW, Lin Y-F, Wu K,\u00a0King Y-C<\/u><\/strong>. “A voltage acceleration lifetime model to predict post-cycling LTDR characteristics of split-gate flash memories”. IEEE International Reliability Physics Symposium Proceedings; 2005; San Jose, CA, United States<\/li>\r\n
                                          4. Chang YW, Chang HW, Lu TC,\u00a0King Y, Ting W, Ku J, Lu CY. “A novel CBCM method free from charge injection induced errors: Investigation into the impact of floating dummy-fills on interconnect capacitance”. IEEE International Conference on Microelectronic Test Structures; 2005; Leuven, Belgium.<\/li>\r\n
                                          5. Lee K-H, Wang S-C,\u00a0King Y-C<\/u><\/strong>. “Novel self-convergent scheme logic-process-based multilevel\/analog EEPROM memory”. Records of the IEEE International Workshop on Memory Technology, Design and Testing; 2005; Taipei, Taiwan<\/li>\r\n
                                          6. Lai C-H,\u00a0King Y-C<\/u><\/strong>, Huang S-Y. “A 1.2V 0.25-\u03bcm clock output pixel sensor with wide dynamic range”. Proceedings of SPIE – The International Society for Optical Engineering; 2005; San Jose, CA, United States<\/li>\r\n
                                          7. Ssu-I Hsieh and\u00a0Ya-Chin King<\/u><\/strong>, \u201cReliability and Memory Characteristics of Sequential Laterally Solidified LTPS TFT with a ONO Stack Gate Dielectric\u201d, Proceeding for the 2005 International Conference on Solid State Devices and Materials, Tokyo, Japan<\/li>\r\n
                                          8. Cheng-Hsiao, Liang-Wei Lai, and\u00a0Ya-Chin King<\/u><\/strong>,\u201c A Logarithmic Response CMOS Image Sensor with Parasitic PNP BJT\u201d,Proceeding for the 2005 International Conference on Solid State Devices and Materials, pp. 940-941 Tokyo, Japan<\/li>\r\n
                                          9. Wei-Cheng Lin and\u00a0Ya-Chin King<\/u><\/strong>,\u201cReliability Evaluation of 5.2GHz CMOS Receiver\u201d, European Microwave Conference, France, October 2005<\/li>\r\n<\/ol>\r\n

                                            2004<\/u><\/strong><\/p>\r\n

                                              \r\n
                                            1. Lin W-C, Du L-J,\u00a0King Y-C<\/u><\/strong>. “Reliability evaluation and comparison of class-E and class-A power amplifiers with 0.18 \u03bcm CMOS technology”. Annual Proceedings – Reliability Physics (Symposium); 2004; Phoenix, AZ., United States.<\/li>\r\n
                                            2. Lin W-C, Du L-J,\u00a0King Y-C<\/u><\/strong>. “Reliability evaluation of Gilbert Cell mixer based on a hot-carrier stressed device degradation model”. IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers; 2004; Fort Worth, TX, United States.<\/li>\r\n
                                            3. Lin C-I, Lai C-H,\u00a0King Y-C<\/u><\/strong>. “A four transistor CMOS active pixel sensor with high dynamic range operation”. Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits; 2004; Fukuoka, Japan.<\/li>\r\n
                                            4. Hu L-C, Kang A-C, Liu IT, Lin Y-F, Wu K,\u00a0King Y-C<\/u><\/strong>. “Statistical modeling for post-cycling data retention of split-gate flash memories”. Annual Proceedings – Reliability Physics (Symposium); 2004; Phoenix, AZ., United States.<\/li>\r\n
                                            5. Kung-Hong Lee, Meng-Yi Wu, Sen-Hue Dai and\u00a0Ya-Chin King<\/u><\/strong>, \u201cCMOS-process-based ultra high density Flash Memory Cell and Array Architecture\u201d, Proceeding for 2004 International Conference on Solid State Devices and Materials, Tokyo, 2004<\/li>\r\n
                                            6. Cheng-Hsiao Lai, Yueh-Ping Yu,\u00a0Ya-Chin King<\/u><\/strong>, \u201cA New Well Capacity Adjusting Scheme for High Sensitivity, Extended Dynamic Range CMOS Imaging Pixel Sensors\u201d, Proceeding for 2004 International Conference on Solid State Devices and Materials, Tokyo, 2004<\/li>\r\n
                                            7. Meng-yi Wu, Kung-Hong Lee1, Sen-Hue Dai1, Shu-Fen Hu, Ya-Chin King<\/u><\/strong>, \u201cLow Voltage and High Speed Efficient Flash Using Band-to-Band Tunneling Induced Substrate Hot Electron Injection (BBISHE) to Perform Programming.\u201d, Proceeding for 2004 International Conference on Solid State Devices and Materials, Tokyo, 2004<\/li>\r\n<\/ol>\r\n

                                              2003<\/u><\/strong><\/p>\r\n

                                                \r\n
                                              1. Shih-Fang, Chen Ying-Jie Juang, Shi-Yu Huang,\u00a0Ya-Chin King<\/u><\/strong>, \u201cLogarithmic CMOS Image Sensor Through Multi-Resolution Analog-To-Digital Conversion\u201d, International Symposium on VLSI Technology, system and Applications (Hsinchu, Taiwan) , Sept. 2003<\/li>\r\n
                                              2. Lai, H.C.; Zous, N.K.; Tsai, W.J.; Lu, T.C.; Tahui Wang; King, Y.C.; Pan, S.\u201cReliable extraction of interface states from charge pumping method in ultra-thin gate oxide MOSFET’s \u201d, International Conference on Microelectronic Test Structures, March 17 – 20, 2003<\/li>\r\n
                                              3. Lin W-C, Du L-J,\u00a0King Y-C<\/u><\/strong>. “Reliability evaluation of voltage controlled oscillators based on a device degradation sub-circuit model”. IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers; 2003; Philadelphia, PA, United States<\/li>\r\n
                                              4. Chang S, Yang E, Chen T, Huang L, Hsu B, Sung D, Duh J-C, Hung C-W, Huang V,\u00a0King Y-C<\/u><\/strong>and others. “New Buried Bit-line NAND (BiNAND) Flash Memory for Data Storage”. Digest of Technical Papers – Symposium on VLSI Technology; 2003; Kyoto, Japan.<\/li>\r\n
                                              5. Lee K-H,\u00a0King Y-C<\/u><\/strong>. “New Single-poly EEPROM with Cell Size down to 8F2\u00a0for High Density Embedded Nonvolatile Memory Applications”. Digest of Technical Papers – Symposium on VLSI Technology; 2003; Kyoto, Japan<\/li>\r\n
                                              6. Po-Hao Huang, Ya-Chin King<\/u><\/strong>, \u201cOptimization of The Ultra-Low Dark Current CMOS Image Sensor Cell Using n+ Ring Reset\u201d, International Conference on Solid State Devices and Materials, Tokyo, September 2003<\/li>\r\n
                                              7. Wang T, Pan S, Lai HC, Zous NK, Tsai WJ, Lu TC,\u00a0King YC<\/u><\/strong>. “Reliable extraction of interface states from charge pumping method in ultra-thin gate oxide MOSFET’s”. IEEE International Conference on Microelectronic Test Structures; 2003.<\/li>\r\n<\/ol>\r\n

                                                2002<\/u><\/strong><\/p>\r\n

                                                  \r\n
                                                1. Liang-Wei Lai,\u00a0Ya-Chin King<\/u><\/strong>,\u201cA Novel Logarithmic Response CMOS Image Sensor With High Output Voltage Swing and In-pixel Fixed Pattern Noise Reduction\u201d, The Third IEEE Asia Pacific Conference on ASICs, August 2002<\/li>\r\n
                                                2. Hsien-Chun Chang,\u00a0Ya-Chin King<\/u><\/strong>, \u201cTunable Injection Current Compensation Architecture for High Fill-factor Self-buffered Active Pixel Sensor\u201d, The Third IEEE Asia Pacific Conference on ASICs, 6-8 August 2002<\/li>\r\n
                                                3. Sing \u2013Rong Lee,\u00a0Ya-Chin King<\/u><\/strong>, \u201c A New Sampling Scheme for High Sensitive, Extended Dynamic Range CMOS Imaging Pixel Sensors\u201d, 2002 International Conference on Solid State Devices and Materials, Tokyo, September 2002<\/li>\r\n<\/ol>\r\n

                                                  2001<\/u><\/strong><\/p>\r\n

                                                    \r\n
                                                  1. She M,\u00a0King YC<\/u><\/strong>, King TJ, Hu C. “Modeling and design study of nanocrystal memory devices”. Annual Device Research Conference Digest; 2001; Notre Dame, IN. p 139.<\/li>\r\n
                                                  2. Lai CH, Hu LC, Lee HM, Do LJ,\u00a0King YC<\/u><\/strong>. “New stack gate insulator structure reduce FIBL effect obviously”. International Symposium on VLSI Technology, Systems, and Applications, Proceedings; 2001; Hsinchu. p 216.<\/li>\r\n
                                                  3. Hsiu-Yu Cheng, Hsien-Chun Chang, Shing-Rung Li, Liang-Wei Lai, Shuh-Sen Lin and\u00a0Ya-Chin King<\/u><\/strong>, “A New Photodiode Structure with Spacer Window for High Sensitivity 0.35-\u03bcm CMOS Imagers”, 2001 International Conference on Solid State Devices and Materials, Tokyo, September 2001, pp.286-287<\/li>\r\n<\/ol>\r\n

                                                    2000<\/u><\/strong><\/p>\r\n

                                                      \r\n
                                                    1. Amy H.-F. Chou; Yu-Yuan Yao,; Wei-Zhe Wong; Evans Ching-Song Yang, Yen-Sen Wang;\u00a0Ya-Chin King<\/u><\/strong>; Charles Hsu.”New Coupling Ratio Extraction Method for Split Gate Flash Memory.”, Non-volatile Workshop, Montery, U.S.A., 2000, pp. 84-85<\/li>\r\n<\/ol>\r\n

                                                      1999<\/u><\/strong><\/p>\r\n

                                                        \r\n
                                                      1. Yang K,\u00a0King Y-C<\/u><\/strong>, Hu C. “Quantum effect in oxide thickness determination from capacitance measurement”. Digest of Technical Papers – Symposium on VLSI Technology; 1999; Kyoto, Japan.<\/li>\r\n
                                                      2. Amy H.-F. Chou; Evans Ching-Song Yang; Wei-Zhe Wong;\u00a0Ya-Chin King<\/u><\/strong>; Charles Hsu. ” A New-bitline-controlled Self-convergent Multi-level AND type Flash Memory” International Conference on Solid State Device and Materials, pp. 536-537, Tokyo, Japan, 1999.<\/li>\r\n
                                                      3. Amy H.-F. Chou; Wei-Zhe Wong; Evans Ching-Song Yang, Yu-Yuan Yao; Yen-Sen Wang;\u00a0Ya-Chin King<\/u><\/strong>; Charles Hsu., “Comprehensive study of a new self-convergent programming scheme for split gate flash memory.” International Conference on Solid State Device and Materials, pp. 540-541, Tokyo, Japan, 1999.<\/li>\r\n<\/ol>\r\n

                                                        1998<\/u><\/strong><\/p>\r\n

                                                          \r\n
                                                        1. King Y-C<\/u><\/strong>, Kuo C, King T-J, Hu C. “Sub-5 nm multiple-thickness gate oxide technology using oxygen implantation”. Technical Digest – International Electron Devices Meeting; 1998; San Francisco, CA, USA.<\/li>\r\n
                                                        2. King Y-C<\/u><\/strong>, King T-J, Hu C. “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”. Technical Digest – International Electron Devices Meeting; 1998; San Francisco, CA, USA.<\/li>\r\n<\/ol>\r\n

                                                          1997<\/u><\/strong><\/p>\r\n

                                                            \r\n
                                                          1. King Y-C<\/u><\/strong>, Fujioka H, Kamohara S, Lee W-C, Hu C. “AC charge centroid model for quantization of inversion layer in n-MOSFET”. International Symposium on VLSI Technology, Systems, and Applications, Proceedings; 1997; Taipei, Taiwan<\/li>\r\n
                                                          2. Shiro Kamohara;\u00a0Ya-Chin King<\/u><\/strong>; Kai Chen; Dongun Park; Hu C.. “MOSFET carrier mobility model based on the density-of-state at the DC-centroid in the quantized inversion layer.”, International Conference on VLSI and CAD, Seoul, South Korea, 1997. p.171.<\/li>\r\n<\/ol>\r\n

                                                            1996<\/u><\/strong><\/p>\r\n

                                                              \r\n
                                                            1. Fujioka H, Wann HJ, Park DG,\u00a0King YC<\/u><\/strong>, Chyan YF, Oshima M, Hu C. “Tunneling current through MIS structures with ultra-thin insulators”. Materials Research Society Symposium – Proceedings; 1996; San Francisco, CA, USA<\/li>\r\n<\/ol>\r\n

                                                              1995<\/u><\/strong><\/p>\r\n

                                                                \r\n
                                                              1. Zhang G,\u00a0King Y<\/u><\/strong>, Eltoukhy S, Hamdy E, Jing T, Yu P, Hu C. “On-state reliability of amorphous silicon antifuses”. Technical Digest – International Electron Devices Meeting; 1995<\/li>\r\n
                                                              2. Yu B,\u00a0King Y-C<\/u><\/strong>, Pohlman J, Hu C. “Punchthrough transient voltage suppressor for EOS\/ESD protection of low-voltage IC’s”. Electrical Overstress\/Electrostatic Discharge Symposium Proceedings; 1995; Phoenix, AZ, USA.<\/li>\r\n<\/ol>\r\n

                                                                 <\/p>\r\n

                                                                  <\/ol>\r\n","protected":false},"excerpt":{"rendered":"

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