{"id":19,"date":"2018-04-20T21:02:40","date_gmt":"2018-04-20T13:02:40","guid":{"rendered":"http:\/\/well.ee.nthu.edu.tw\/?page_id=19"},"modified":"2024-03-19T17:43:07","modified_gmt":"2024-03-19T09:43:07","slug":"%e7%a0%94%e7%a9%b6%e8%a8%88%e7%95%ab","status":"publish","type":"page","link":"https:\/\/starlab.ee.nthu.edu.tw\/?page_id=19","title":{"rendered":"\u7814\u7a76\u8a08\u756b"},"content":{"rendered":"

\u6b77\u5e74\u8a08\u756b<\/span><\/strong><\/h3>\n\n\n\n\n\t\n\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t\n\t
\u7de8\u865f<\/th>\u8a08\u756b\u671f\u9593<\/th>\u8a08\u756b\u540d\u7a31<\/th>\u6838\u5b9a\u55ae\u4f4d<\/th>\u4e3b\u6301\u4eba<\/th>\n<\/tr>\n<\/thead>\n
1<\/td>114-117<\/td>AQHE-\u7a81\u7834\u7b97\u529b\u6975\u9650\uff1a\u65b0\u4e16\u4ee3\u9ad8\u6548\u80fd\u904b\u7b97\u534a\u5c0e\u9ad4\u6280\u8853\u7814\u767c<\/td>\u570b\u79d1\u6703\u3001\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u5f90\u78a9\u9d3b , \u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
2<\/td>115-117<\/td>A CMOS Logic Compatible High Density 1.5T FinFET Dielectric RRAM in Embedded Applications<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
3<\/td>115-117 <\/td>On-Chip Differential Plasma Charge Detector for PID and ESD Process Monitoring in TSMC FinFET CMOS Process<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
4<\/td>115-117 <\/td>A test circuit that enables mass MOS capacitance measurements within a single scribe-line<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u91d1\u96c5\u7434 , \u6797\u5d07\u69ae<\/td>\n<\/tr>\n
5<\/td>114-115<\/td>AI-Quantum-EUV (AQE) \u53f0\u7a4d\u6e05\u83ef\u7522\u5b78\u5927\u806f\u76df<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u672c\u5805 ,\u6797\u5d07\u69ae , \u91d1\u96c5\u7434, \u5f35\u9451\u5143<\/td>\n<\/tr>\n
6<\/td>114-117<\/td>\u4e92\u88dc\u5f0f\u7269\u7406\u4e0d\u53ef\u8907\u88fd\u51fd\u6578\u6a21\u7d44\u8a2d\u8a08\u53ca\u958b\u767c<\/td>\u570b\u79d1\u6703<\/td>\u91d1\u96c5\u7434, \u6797\u5d07\u69ae<\/td>\n<\/tr>\n
7<\/td>113-116<\/td>\u7a4d\u9ad4\u5316\u4e8c\u7dad\u6750\u6599\u6c23\u9ad4\u611f\u6e2c\u9663\u5217\u6a21\u7d44\u958b\u767c<\/td>\u570b\u79d1\u6703<\/td>\u91d1\u96c5\u7434 , \u6797\u5d07\u69ae<\/td>\n<\/tr>\n
8<\/td>113-115<\/td>A High Density 3D Stackable Via RRAM Latch for Computing in Memory SOC Applications <\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
9<\/td>113-115<\/td>On-Chip In-situ Detector for PID and ESD Monitoring in Advanced FinFET CMOS and BCD Processes <\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
10<\/td>113-115<\/td>RRAM statistical characterization for analytical & numerical model development to improve RRAM reliability & performance<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae<\/td>\n<\/tr>\n
11<\/td>112-115<\/td>\u985e\u795e\u7d93\u7db2\u8def\u904b\u7b97\u6676\u7247\u4e4b\u9ad8\u5bc6\u5ea6\u975e\u63ee\u767c\u6027\u96fb\u963b\u5f0f\u8a18\u61b6\u908f\u8f2f\u9598<\/td>\u570b\u79d1\u6703<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
12<\/td>112-115<\/td>High Resistance Via (HRV) Matrix & High Capacitance of VIA PIN Array Capacitor (VPAC) in FinFET Technology Platforms<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u91d1\u96c5\u7434 , \u6797\u5d07\u69ae <\/td>\n<\/tr>\n
13<\/td>112-114<\/td>A High Density 3D Wing-Shaped Via RRAM Memory in Fully Compatible FinFET Process<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
14<\/td>112-114<\/td>\u4e09\u7dad\u5806\u758a\u8d85\u9ad8\u5bc6\u5ea6\u5d4c\u5165\u5f0f\u975e\u63ee\u767c\u8a18\u61b6\u9ad4\u6280\u8853(II)<\/td>\u570b\u79d1\u6703<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
15<\/td>111-112<\/td>\u61c9\u7528\u65bc\u9ad8\u901f\u985e\u795e\u7d93\u7db2\u8def\u6676\u7247\u7684CMOS \u88fd\u7a0b\u76f8\u5bb9\u4e4b\u4eba\u5de5\u7a81\u89f8\u5143\u4ef6<\/td>\u570b\u79d1\u6703<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
16<\/td>111-113<\/td>Low Voltage One-Time-Programmable(OTP) Memory for HPC Logic Platform<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
17<\/td>111-112<\/td>Development of High-Capacitance MIM Structure and New Capacitance Characterization Techniques<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
18<\/td>110-112<\/td>\u4e09\u7dad\u5806\u758a\u8d85\u9ad8\u5bc6\u5ea6\u5d4c\u5165\u5f0f\u975e\u63ee\u767c\u8a18\u61b6\u9ad4\u6280\u8853<\/td>\u570b\u79d1\u6703<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
19<\/td>110-111<\/td>\u4e09\u7dad\u96fb\u5b50\u5fae\u611f\u6e2c\u5143\u4ef6\u9663\u5217\u7684\u7814\u7a76\u8207\u958b\u767c<\/td>\u570b\u79d1\u6703<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
20<\/td>110-113<\/td>\u61c9\u7528\u65bc\u524d\u77bb\u5fae\u5f71\u7cfb\u7d71\u4e2d\u6676\u5713\u4e0a\u81ea\u6211\u9a45\u52d5\u4e4b\u7121\u7dda\u5149\u6e90\u611f\u6e2c\u6a21\u7d44<\/td>\u570b\u79d1\u6703<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
21<\/td>110-113<\/td>\u4ee5\u4e8c\u7dad\u6750\u6599\u70ba\u57fa\u790e\u7684ppb\u7b49\u7d1a\u6c23\u9ad4\u611f\u6e2c\u5143\u4ef6\u8207\u96fb\u8def\u6a21\u7d44\u4e4b\u958b\u767c\u53ca\u5be6\u969b\u5834\u57df\u61c9\u7528<\/td>\u570b\u79d1\u6703<\/td>\u91d1\u96c5\u7434 , \u95d5\u90c1\u502b<\/td>\n<\/tr>\n
22<\/td>110-111<\/td>Development of High-Capacitance MIM\/MOM and New Capacitance Characterization Techniques<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
23<\/td>109-112<\/td>Memory-Logic Hybrid Gate with 3D-Stackable Complementary Latches for FinFET-Based Neural Networks<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
24<\/td>109-112<\/td>FINFET Technology Benyond 16nm-Device and Process Reliabililty Improvement<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434 , \u95d5\u90c1\u502b<\/td>\n<\/tr>\n
25<\/td>108-113<\/td>\u524d\u77bb\u6280\u8853\u7522\u5b78\u5408\u4f5c\u8a08\u756b-\u9858\u666f\u5be6\u73fe\u8a08\u756b:\u4ee5\u524d\u77bb\u6027\u8a08\u7b97\u6cd5\u3001\u6750\u6599\u3001\u8a08\u91cf\u6cd5\u63a8\u52d5\u534a\u5c0e\u9ad4\u6280\u8853<\/td>\u570b\u79d1\u6703\u3001\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u672c\u5805 , \u6797\u5d07\u69ae , \u91d1\u96c5\u7434 <\/td>\n<\/tr>\n
26<\/td>108-109<\/td>Logic Compatible Differential MTP Memory Cells on FinFET Technologies<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
27<\/td>108-109<\/td>FINFET Technology Beyond16nm \u2013 Monitor Methodology and Devices of Plasma Antenna Effect<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
28<\/td>108-109<\/td>FINFET Technology Beyond 16nm - FinFET Dielectric (FIND) RRAM for 7nm Technology Node<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
29<\/td>107-108<\/td>Development of Twin Mode NV Logic Gates by FinFET CMOS Logic Process<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
30<\/td>107-110<\/td>\u61c9\u7528\u65bc\u9c2d\u5f0f\u96fb\u6676\u9ad4\u88fd\u7a0b\u5e73\u53f0\u4e4b\u5d4c\u5165\u5f0f\u8755\u523b\u5b54\u96fb\u963b\u5f0f\u8a18\u61b6\u9ad4\u5143\u4ef6\u3001\u9663\u5217\u53ca\u77fd\u667a\u8ca1\u958b\u767c<\/td>\u570b\u79d1\u6703<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434<\/td>\n<\/tr>\n
31<\/td>107-110<\/td>\u7d50\u5408\u81ea\u6211\u4fee\u6b63\u5143\u4ef6\u4e4b\u4e0d\u53ef\u8907\u88fd\u51fd\u6578\u975c\u614b\u96a8\u6a5f\u5b58\u53d6\u8a18\u61b6\u9ad4\u7814\u7a76<\/td>\u570b\u79d1\u6703<\/td>\u91d1\u96c5\u7434<\/td>\n<\/tr>\n
32<\/td>107-110<\/td>\u76f8\u5bb9\u65bc\u91d1\u6c27\u534a\u5c0e\u9ad4\u88fd\u7a0b\u4e4b\u53ef\u8abf\u8b8a\u8fd1\u7d05\u5916\u5149\u611f\u6e2c\u5143\u4ef6<\/td>\u570b\u79d1\u6703<\/td>\u91d1\u96c5\u7434<\/td>\n<\/tr>\n
33<\/td>106-108<\/td>FINFET Technology Benyond 16nm-Device and Process Reliabililty Improvement<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434 , \u95d5\u90c1\u502b<\/td>\n<\/tr>\n
34<\/td>105-107<\/td>Development of FINFET Dielectric (FIND) RRAM in FinFET COMS Logic Process<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434 <\/td>\n<\/tr>\n
35<\/td>104-106<\/td>FINFET Technology Benyond 16nm-Device and Process Reliabililty Improvement<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434 , \u95d5\u90c1\u502b<\/td>\n<\/tr>\n
36<\/td>104-107<\/td>\u61c9\u7528\u65bc\u9c2d\u5f0f\u5834\u6548\u96fb\u6676\u9ad4\u7684\u4e00\u6b21\u5beb\u5165\u8a18\u61b6\u9ad4\u53ca\u88fd\u7a0b\u96fb\u6f3f\u5075\u6e2c\u5143\u4ef6<\/td>\u79d1\u6280\u90e8<\/td>\u6797\u5d07\u69ae<\/td>\n<\/tr>\n
37<\/td>104-107<\/td>\u5948\u7c73\u7d1a\u9c2d\u5f0f\u96fb\u6676\u9ad4\u5bc4\u751f\u6548\u61c9\u76e3\u6e2c\u6280\u8853\u8207\u964d\u4f4e\u5bc4\u751f\u6548\u61c9\u4e4b\u8a2d\u8a08\u7814\u7a76<\/td>\u79d1\u6280\u90e8<\/td>\u91d1\u96c5\u7434<\/td>\n<\/tr>\n
38<\/td>104-106<\/td>\u5148\u9032\u88fd\u7a0b\u4e4b\u65b0\u578b\u9ad8\u6548\u80fd\u63a5\u89f8\u9ede\u96fb\u963b\u5f0f\u8a18\u61b6\u9ad4\u80de\u8a2d\u8a08\u8207\u958b\u767c<\/td>\u79d1\u6280\u90e8<\/td>\u6797\u5d07\u69ae<\/td>\n<\/tr>\n
39<\/td>104-105<\/td>Embedded Contact RRAM(CRRAM) on 28nm HKMG CMOS Logic Platform<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434 <\/td>\n<\/tr>\n
40<\/td>103-106<\/td>\u61c9\u7528\u65bc\u4e09\u7dad\u7a4d\u9ad4\u96fb\u8def\u4e4b\u78c1\u611f\u61c9\u7121\u7dda\u9023\u7d50\u6280\u8853\u958b\u767c\u8207\u7814\u7a76<\/td>\u570b\u79d1\u6703<\/td>\u91d1\u96c5\u7434<\/td>\n<\/tr>\n
41<\/td>103-104<\/td>\u5148\u9032\u88fd\u7a0b\u4e4b\u65b0\u578b\u9ad8\u6548\u80fd\u63a5\u89f8\u9ede\u96fb\u963b\u5f0f\u8a18\u61b6\u9ad4\u80de\u8a2d\u8a08\u8207\u958b\u767c (I)<\/td>\u570b\u79d1\u6703<\/td>\u6797\u5d07\u69ae<\/td>\n<\/tr>\n
42<\/td>103-104<\/td>FINFET Technology Benyond 16nm-Device and Process Reliabililty Improvement<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434 , \u95d5\u90c1\u502b<\/td>\n<\/tr>\n
43<\/td>102-103<\/td>\u61c9\u7528\u65bc\u4eff\u795e\u7d93\u5143\u9023\u7d50\u4e4b\u7121\u7dda\u96fb\u78c1\u8a0a\u865f\u50b3\u905e\u6280\u8853\u958b\u767c (I)<\/td>\u570b\u79d1\u6703<\/td>\u91d1\u96c5\u7434<\/td>\n<\/tr>\n
44<\/td>102-103<\/td>Logic Non-volatile Memory Cells for 28nm and beyond HKMG CMOS technologies<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434 <\/td>\n<\/tr>\n
45<\/td>102-103<\/td>\u5167\u5d4c\u5f0f\u63a5\u89f8\u9ede\u96fb\u963b\u5f0f\u8a18\u61b6\u9ad4\u65bc 40 \u5948\u7c73\u4e92\u88dc\u5f0f\u91d1\u6c27\u534a\u908f\u8f2f\u88fd\u7a0b\u5e73\u53f0<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u516c\u53f8<\/td><\/td>\n<\/tr>\n
46<\/td>102-103<\/td>Embedded Contact RRAM on 40nm CMOS Logic Platform<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u516c\u53f8<\/td>\u6797\u5d07\u69ae , \u91d1\u96c5\u7434 <\/td>\n<\/tr>\n
47<\/td>102<\/td>\u975e\u7dda\u6027\u96d9\u5143\u6c27\u5316\u7269\u96fb\u963b\u5f0f\u8a18\u61b6\u9ad4\u958b\u767c<\/td>\u5de5\u696d\u6280\u8853\u7814\u7a76\u9662<\/td><\/td>\n<\/tr>\n
48<\/td>102<\/td>\u667a\u6167\u96fb\u5b50\u570b\u5bb6\u578b\u79d1\u6280\u8a08\u756b\u7814\u7a76\u6210\u679c\u7522\u5b78\u6a4b\u63a5\u8a08\u756b<\/td>\u570b\u79d1\u6703<\/td><\/td>\n<\/tr>\n
49<\/td>101-102<\/td>\u63a5\u89f8\u9ede\u96fb\u963b\u5f0f\u8a18\u61b6\u9ad4\u96a8\u6a5f\u96fb\u5831\u5f0f\u96dc\u8a0a\u4e4b\u5206\u6790\u8207\u771f\u5be6\u4e82\u6578\u7522\u751f\u5668\u8a2d\u8a08\u7814\u7a76<\/td>\u570b\u79d1\u6703<\/td>\u6797\u5d07\u69ae<\/td>\n<\/tr>\n
50<\/td>101-102<\/td>\u65b0\u578b HKMG \u63a5\u89f8\u9ede\u96fb\u963b\u5f0f (CRRAM) \u8a18\u61b6\u5143\u4ef6\u53ca\u6280\u8853\u4e4b\u958b\u767c<\/td>\u5de5\u696d\u6280\u8853\u7814\u7a76\u9662<\/td><\/td>\n<\/tr>\n
51<\/td>100-102<\/td>\u5b50\u8a08\u756b\u4e8c\uff1a\u9ad8\u5bc6\u5ea6\u63a5\u89f8\u9ede\u96fb\u963b\u5f0f\u8a18\u61b6\u80de\u8a2d\u8a08\u53ca\u9a45\u52d5\u96fb\u6676\u9ad4\u958b\u767c ( \u2161 )<\/td>\u570b\u79d1\u6703<\/td>\u91d1\u96c5\u7434<\/td>\n<\/tr>\n
52<\/td>100-102<\/td>\u7e3d\u8a08\u756b ( \u2161 )<\/td>\u570b\u79d1\u6703<\/td>\u91d1\u96c5\u7434<\/td>\n<\/tr>\n
53<\/td>100-102<\/td>\u7121\u7dda\u611f\u6e2c\u7db2\u8def\u61c9\u7528\u4e4b\u6574\u5408\u5f0f\u74b0\u5883\u611f\u6e2c\u96fb\u8def\u8207\u5132\u5b58\u88dd\u7f6e\u6676\u7247\u958b\u767c<\/td>\u570b\u79d1\u6703<\/td><\/td>\n<\/tr>\n
54<\/td>100-102<\/td>\u65b0\u578b\u9ad8\u5bc6\u5ea6\u63a5\u89f8\u9ede\u96fb\u963b\u5f0f\u8a18\u61b6\u9ad4\u9663\u5217\u958b\u767c\uff0d\u5b50\u8a08\u756b\u4e8c\uff1a\u9ad8\u5bc6\u5ea6\u63a5\u89f8\u9ede\u96fb\u963b\u5f0f\u8a18\u61b6\u80de\u8a2d\u8a08\u53ca\u9a45\u52d5\u96fb\u6676\u9ad4\u958b\u767c ( \u2161 )<\/td>\u570b\u79d1\u6703<\/td><\/td>\n<\/tr>\n
55<\/td>100-102<\/td>\u65b0\u578b\u9ad8\u5bc6\u5ea6\u63a5\u89f8\u9ede\u96fb\u963b\u5f0f\u8a18\u61b6\u9ad4\u9663\u5217\u958b\u767c\uff0d\u7e3d\u8a08\u756b ( \u2161 )<\/td>\u570b\u79d1\u6703<\/td><\/td>\n<\/tr>\n
56<\/td>100-101<\/td>\u5b50\u8a08\u756b\u4e00\uff1a\u65b0\u578b\u63a5\u89f8\u9ede\u96fb\u963b\u5f0f\u8a18\u61b6\u5c64\u958b\u767c\u53ca\u6700\u4f73\u5316\u5206\u6790 ( \u2161 )<\/td>\u570b\u79d1\u6703<\/td>\u6797\u5d07\u69ae<\/td>\n<\/tr>\n
57<\/td>100-101<\/td>\u964d\u4f4e\u8584\u819c\u96fb\u6676\u9ad4\u5149\u6f0f\u96fb\u6d41\u7814\u7a76<\/td>\u5947\u7f8e\u96fb\u5b50<\/td><\/td>\n<\/tr>\n
58<\/td>100-101<\/td>600V-900V \u8d85\u7d1a\u63a5\u9762 LDMOS \u5143\u4ef6\u8a2d\u8a08\u8207\u7279\u6027\u6a21\u64ec<\/td>\u53f0\u7063\u534a\u5c0e\u9ad4\u80a1\u4efd\u6709\u9650\u516c\u53f8<\/td><\/td>\n<\/tr>\n
59<\/td>100-101<\/td>CCG MTP \u4e4b\u5143\u4ef6\u8207\u6676\u7247\u8a2d\u8a08\u53ca\u53ef\u9760\u6027\u7814\u7a76\u8a08\u756b<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u516c\u53f8<\/td><\/td>\n<\/tr>\n
60<\/td>99-103<\/td>\u4f4e\u6f0f\u96fb\u53ca\u4f4e\u96fb\u5bb9\u4e4b\u66ab\u614b\u96fb\u58d3\u6291\u5236\u5668\u6574\u5408\u5143\u4ef6<\/td>\u5ee3\u958e\u79d1\u6280<\/td><\/td>\n<\/tr>\n
61<\/td>99-102<\/td>\u7121\u7dda\u611f\u6e2c\u7db2\u8def\u61c9\u7528\u4e4b\u6574\u5408\u5f0f\u74b0\u5883\u611f\u6e2c\u96fb\u8def\u8207\u5132\u5b58\u88dd\u7f6e\u6676\u7247\u958b\u767c<\/td>\u570b\u79d1\u6703<\/td>\u91d1\u96c5\u7434<\/td>\n<\/tr>\n
62<\/td>99-102<\/td>Capacitance Measurement Technique and Interface State Analysis on Small-geometric HKMG Devices<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u516c\u53f8<\/td><\/td>\n<\/tr>\n
63<\/td>99-100<\/td>\u5b50\u8a08\u756b\u4e00\uff1a\u65b0\u578b\u63a5\u89f8\u9ede\u96fb\u963b\u5f0f\u8a18\u61b6\u5c64\u958b\u767c\u53ca\u6700\u4f73\u5316\u5206\u6790 (I)<\/td>\u570b\u79d1\u6703<\/td>\u6797\u5d07\u69ae<\/td>\n<\/tr>\n
64<\/td>99-100<\/td>\u5b50\u8a08\u756b\u4e8c\uff1a\u9ad8\u5bc6\u5ea6\u63a5\u89f8\u9ede\u96fb\u963b\u5f0f\u8a18\u61b6\u80de\u8a2d\u8a08\u53ca\u9a45\u52d5\u96fb\u6676\u9ad4\u958b\u767c (I)<\/td>\u570b\u79d1\u6703<\/td>\u91d1\u96c5\u7434<\/td>\n<\/tr>\n
65<\/td>99-100<\/td>\u7e3d\u8a08\u756b (I)<\/td>\u570b\u79d1\u6703<\/td>\u91d1\u96c5\u7434<\/td>\n<\/tr>\n
66<\/td>99<\/td>\u5148\u9032\u9762\u677f\u6280\u8853\u4e4b\u65b0\u61c9\u7528\u958b\u767c<\/td>\u589e\u80fd\u8a08\u756b<\/td><\/td>\n<\/tr>\n
67<\/td>99<\/td>3DIC \u88fd\u7a0b\u9020\u6210\u4e4b\u5143\u4ef6\u6216\u7d50\u69cb\u5931\u6548\u7814\u7a76<\/td>\u5de5\u696d\u6280\u8853\u7814\u7a76\u9662<\/td><\/td>\n<\/tr>\n
68<\/td>98-99<\/td>\u5b50\u8a08\u756b\u4e8c\uff1a\u61c9\u7528\u65bc DNA \u5b9a\u5e8f\u53ca\u764c\u75c7\u514d\u75ab\u53cd\u61c9\u6aa2\u6e2c\u4e4b\u4e3b\u52d5\u5f0f\u5fae\u7dda\u5708\u9663\u5217 (3\/3)<\/td>\u570b\u79d1\u6703<\/td>\u6797\u5d07\u69ae<\/td>\n<\/tr>\n
69<\/td>98-99<\/td>\u5b50\u8a08\u756b\u4e00\uff1a DNA \u5b9a\u5e8f\u53ca\u764c\u75c7\u514d\u75ab\u53cd\u61c9\u6aa2\u6e2c\u4e4b\u4f4e\u6eab\u591a\u6676\u77fd\u9762\u677f\u5f71\u50cf\u611f\u6e2c\u5668 (3\/3)<\/td>\u570b\u79d1\u6703<\/td>\u91d1\u96c5\u7434<\/td>\n<\/tr>\n
70<\/td>98-99<\/td>\u7e3d\u8a08\u756b (3\/3)<\/td>\u570b\u79d1\u6703<\/td>\u91d1\u96c5\u7434<\/td>\n<\/tr>\n
71<\/td>98<\/td>\u5148\u9032\u9762\u677f\u6280\u8853\u4e4b\u65b0\u61c9\u7528\u958b\u767c<\/td>\u589e\u80fd\u8a08\u756b<\/td><\/td>\n<\/tr>\n
72<\/td>98<\/td>Photo-TFT \u4e4b\u5149 sensitivity \u63d0\u6607\u8207 photo sersor array \u5468\u908a\u96fb\u8def\u8a2d\u8a08<\/td>\u5de5\u696d\u6280\u8853\u7814\u7a76\u9662<\/td><\/td>\n<\/tr>\n
73<\/td>97-99<\/td>PCAF OTP \u4e4b\u5143\u4ef6\u8207\u6676\u7247\u8a2d\u8a08\u53ca\u53ef\u9760\u6027\u7814\u7a76<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u516c\u53f8<\/td><\/td>\n<\/tr>\n
74<\/td>97-98<\/td>\u5b50\u8a08\u756b\u4e8c\uff1a\u61c9\u7528\u65bc DNA \u5b9a\u5e8f\u53ca\u764c\u75c7\u514d\u75ab\u53cd\u61c9\u6aa2\u6e2c\u4e4b\u4e3b\u52d5\u5f0f\u5fae\u7dda\u5708\u9663\u5217 (2\/3)<\/td>\u570b\u79d1\u6703<\/td>\u6797\u5d07\u69ae<\/td>\n<\/tr>\n
75<\/td>96-97<\/td>\u5b50\u8a08\u756b\u4e8c\uff1a\u61c9\u7528\u65bc DNA \u5b9a\u5e8f\u53ca\u764c\u75c7\u514d\u75ab\u53cd\u61c9\u6aa2\u6e2c\u4e4b\u4e3b\u52d5\u5f0f\u5fae\u7dda\u5708\u9663\u5217 (1\/3)<\/td>\u570b\u79d1\u6703<\/td>\u6797\u5d07\u69ae<\/td>\n<\/tr>\n
76<\/td>95-96<\/td>Photo-detector for Optical Touch Panel System<\/td>\u53cb\u9054\u5149\u96fb<\/td><\/td>\n<\/tr>\n
77<\/td>95-96<\/td>Study of 2T P-channel MTP Cell with BBHH Erase Operation<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u516c\u53f8<\/td><\/td>\n<\/tr>\n
78<\/td>95-96<\/td>CMOS \u5f71\u50cf\u611f\u6e2c\u5668\u4e4b\u65b0\u578b\u50cf\u7d20\u53ca\u9663\u5217\u67b6\u69cb\u8a2d\u8a08<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u516c\u53f8<\/td><\/td>\n<\/tr>\n
79<\/td>95<\/td>\u4f4e\u6eab\u591a\u6676\u77fd\u975e\u63ee\u767c\u6027\u8a18\u61b6\u9ad4\u4e4b\u958b\u767c\u8207\u5e73\u9762\u986f\u793a\u5668\u7522\u54c1\u61c9\u7528\u6027\u8a55\u4f30<\/td>\u5de5\u7814\u9662<\/td><\/td>\n<\/tr>\n
80<\/td>95<\/td>\u61c9\u7528\u65bc\u9ad8\u89e3\u6790\u5ea6\u4f4e\u6eab\u591a\u6676\u77fd\u8584\u819c\u96fb\u6676\u9ad4\u6db2\u6676\u986f\u793a\u5668\u4e4b One-Time Programming \u8a18\u61b6\u9ad4\u958b\u767c<\/td>\u7d71\u5bf6\u5149\u96fb<\/td><\/td>\n<\/tr>\n
81<\/td>94-95<\/td>\u5948\u7c73\u5148\u9032\u5d4c\u5165\u5f0f\u5feb\u9583\u8a18\u61b6\u9ad4\u958b\u767c<\/td>\u570b\u79d1\u6703<\/td>\u6797\u5d07\u69ae<\/td>\n<\/tr>\n
82<\/td>94-95<\/td>\u4f4e\u96fb\u58d3\u3001\u4f4e\u96fb\u5bb9\u7a81\u6ce2\u6291\u5236\u5668\u4e4b\u8a2d\u8a08\u3001\u88fd\u4f5c\u8207\u91cf\u6e2c<\/td>\u53f0\u7063\u901a\u7528\u5668\u6750<\/td><\/td>\n<\/tr>\n
83<\/td>94-95<\/td>\u592a\u7a7a\u7d1a CMOS \u5f71\u50cf\u611f\u6e2c\u5668\u6a21\u7d44\u767c\u5c55\u8a08\u756b<\/td>\u570b\u5bb6\u5be6\u9a57\u7814\u7a76\u9662<\/td><\/td>\n<\/tr>\n
84<\/td>94-95<\/td>\u5c04\u983b\u7a4d\u6975\u96fb\u8def\u53ca\u50b3\u8f38\u7cfb\u7d71\u53ef\u9760\u5ea6\u5206\u6790\u7814\u7a76<\/td>\u570b\u79d1\u6703<\/td><\/td>\n<\/tr>\n
85<\/td>94<\/td>\u4f4e\u6eab\u591a\u6676\u77fd\u4e4b\u5148\u9032\u9598\u6975\u4ecb\u96fb\u5c64\u958b\u767c<\/td>\u5de5\u7814\u9662<\/td><\/td>\n<\/tr>\n
86<\/td>93-95<\/td>Embedded Flash Memory Project<\/td>\u53f0\u7063\u7a4d\u9ad4\u96fb\u8def\u516c\u53f8<\/td><\/td>\n<\/tr>\n
87<\/td>92-93<\/td>Fabrication Technology, Device Physics of MITT \u5b50\u8a08\u756b : Nano-Memory Device by MITT<\/td>\u806f\u5927\u5948\u7c73\u4e2d\u5fc3<\/td><\/td>\n<\/tr>\n
88<\/td>92-93<\/td>\u5408\u4f5c\u958b\u767c 0.18um \u4e92\u88dc\u5f0f\u91d1\u6c27\u534a\u4e3b\u52d5\u5f71\u50cf\u611f\u6e2c\u5668\u6280\u8853<\/td>\u5a01\u9a30\u5149\u96fb<\/td><\/td>\n<\/tr>\n
89<\/td>92-93<\/td>\u5782\u76f4\u5f0f\u5206\u96e2\u9598\u5feb\u9583\u8a18\u61b6\u9ad4\u4e4b\u8a2d\u8a08\u88fd\u7a0b\u53ca\u53ef\u9760\u6027\u7814\u7a76 (3\/3)<\/td>\u570b\u79d1\u6703<\/td>\u5f90\u6e05\u7965<\/td>\n<\/tr>\n
90<\/td>92<\/td>\u5948\u7c73\u7d1a\u91d1\u6c27\u534a\u5143\u4ef6\u9ad8\u4ecb\u96fb\u9598\u6975\u4e4b\u8a2d\u8a08\u53ca\u53ef\u9760\u6027\u7814\u7a76<\/td>\u5de5\u7814\u9662<\/td><\/td>\n<\/tr>\n
91<\/td>91-93<\/td>\u6574\u5408\u578b\u9ad8\u6548\u80fd\u4e92\u88dc\u5f0f\u91d1\u6c27\u534a\u5f71\u50cf\u611f\u6e2c\u5668\u4e4b\u958b\u767c\u8207\u8a2d\u8a08<\/td>\u570b\u79d1\u6703<\/td><\/td>\n<\/tr>\n
92<\/td>91-92<\/td>\u5782\u76f4\u5f0f\u5206\u96e2\u9598\u5feb\u9583\u8a18\u61b6\u9ad4\u4e4b\u8a2d\u8a08\u88fd\u7a0b\u53ca\u53ef\u9760\u6027\u7814\u7a76 (2\/3)<\/td>\u570b\u79d1\u6703<\/td>\u5f90\u6e05\u7965<\/td>\n<\/tr>\n
93<\/td>90-92<\/td>\u9ad8\u901f\u7de8\u78bc\u3001\u9ad8\u6548\u7387\u5341\u5104\u4f4d\u5143\u5feb\u9583\u5f0f\u8a18\u61b6\u9ad4\u7814\u767c<\/td>\u570b\u79d1\u6703 \/ \u529b\u65fa\u96fb\u5b50<\/td><\/td>\n<\/tr>\n
94<\/td>90-91<\/td>\u5782\u76f4\u5f0f\u5206\u96e2\u9598\u5feb\u9583\u8a18\u61b6\u9ad4\u4e4b\u8a2d\u8a08\u88fd\u7a0b\u53ca\u53ef\u9760\u6027\u7814\u7a76 (1\/3)<\/td>\u570b\u79d1\u6703<\/td>\u5f90\u6e05\u7965<\/td>\n<\/tr>\n
95<\/td>90-91<\/td>\u5b50\u8a08\u756b\u4e00 : \u667a\u6167\u578b IGBT \u4e4b\u8a2d\u8a08\u53ca\u88fd\u4f5c (2\/2)<\/td>\u570b\u79d1\u6703<\/td>\u5f90\u6e05\u7965<\/td>\n<\/tr>\n
96<\/td>90<\/td>\u5948\u7c73\u91d1\u6c27\u534a\u5834\u6548\u96fb\u6676\u9ad4\u4e4b\u65b0\u9598\u7d50\u69cb\u53ca\u9598\u6750\u6599\u91d1\u6c27\u534a\u5834\u6548\u96fb\u6676\u9ad4\u4e4b\u8a2d\u8a08\u8207\u6700\u4f73\u5316<\/td>\u570b\u79d1\u6703<\/td><\/td>\n<\/tr>\n
97<\/td>89-90<\/td>\u5b50\u8a08\u756b\u4e00 : \u667a\u6167\u578b IGBT \u4e4b\u8a2d\u8a08\u53ca\u88fd\u4f5c (1\/2)<\/td>\u570b\u79d1\u6703<\/td>\u5f90\u6e05\u7965<\/td>\n<\/tr>\n
98<\/td>89-90<\/td>\u8a08\u756b\u540d\u7a31\uff1a\u5b50\u8a08\u756b\u4e09 : \u5728 BCD \u6280\u8853\u4e2d\u4e4b\u5074\u5411\u64f4\u6563\u5f0f\u91d1\u6c27\u534a\u5143\u4ef6\u4e4b\u6700\u4f73\u5316\u8a2d\u8a08\u8207\u88fd\u9020<\/td>\u570b\u79d1\u6703<\/td>\u5f90\u6e05\u7965<\/td>\n<\/tr>\n
99<\/td>89-90<\/td>\u8a08\u756b\u540d\u7a31\uff1a\u7e3d\u8a08\u756b : \u61c9\u7528\u65bc\u985e\u6bd4\u96fb\u8def\u4e4b\u6574\u5408\u5f0f\u96d9\u6975\u6027 \/ \u4e92\u88dc\u91d1\u6c27\u534a\u5143\u4ef6 \/ \u64f4\u6563\u5f0f\u91d1\u6c27\u534a\u5143\u4ef6\u6280\u8853\u4e4b\u958b\u767c<\/td>\u570b\u79d1\u6703<\/td>\u5f90\u6e05\u7965<\/td>\n<\/tr>\n
100<\/td>89<\/td>BiNOR Flash Memory \u4e4b\u6280\u8853\u958b\u767c<\/td>\u529b\u65fa\u96fb\u5b50<\/td><\/td>\n<\/tr>\n
101<\/td>89<\/td>\u7531\u7406\u8ad6\u6a21\u578b\u5c0d\u6beb\u5fae\u9ede\u8a18\u61b6\u9ad4\u5143\u4ef6\u4e4b\u8a2d\u8a08\u53ca\u6700\u4f73\u5316\u7814\u7a76<\/td>\u570b\u79d1\u6703<\/td><\/td>\n<\/tr>\n
102<\/td>88-92<\/td>CMOS Active Pixel Image Sensor \u4e4b\u6280\u8853\u958b\u767c<\/td>\u96d9\u6f22\u79d1\u6280<\/td><\/td>\n<\/tr>\n
103<\/td>88-89<\/td>\u8a08\u756b\u540d\u7a31\uff1a\u5b50\u8a08\u756b\u4e00 : \u667a\u6167\u578b IGBT \u4e4b\u8a2d\u8a08\u8207\u88fd\u4f5c<\/td>\u570b\u79d1\u6703<\/td>\u5f90\u6e05\u7965<\/td>\n<\/tr>\n
104<\/td>88-89<\/td>\u8a08\u756b\u540d\u7a31\uff1a\u5b50\u8a08\u756b\u4e09 : \u5728 BCD \u6280\u8853\u4e2d\u4e4b\u5074\u5411\u64f4\u6563\u5f0f\u91d1\u6c27\u534a\u5143\u4ef6\u4e4b\u6700\u4f73\u5316\u8a2d\u8a08\u8207\u88fd\u9020<\/td>\u570b\u79d1\u6703<\/td>\u5f90\u6e05\u7965<\/td>\n<\/tr>\n
105<\/td>88-90<\/td>\u8a08\u756b\u540d\u7a31\uff1a\u7e3d\u8a08\u756b<\/td>\u570b\u79d1\u6703<\/td>\u5f90\u6e05\u7965<\/td>\n<\/tr>\n
106<\/td>88<\/td>\u9ad8\u4ecb\u96fb\u91d1\u6c27\u534a\u5143\u4ef6\u4e4b\u8a2d\u8a08\u88fd\u7a0b\u53ca\u53ef\u9760\u6027\u7814\u7a76<\/td>\u570b\u79d1\u6703<\/td><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n","protected":false},"excerpt":{"rendered":"

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